FPD BEAM TEST DAQ

The plan for the engineering run is to have scintillation counters in all the vertical pots and scintillating fiber detectors in two pots. We use scintillation counter coincidences to trigger the fiber detectors and record their ADC information. Each fiber detector is readout through 7 multianode pmts (16 anodes each, Hamamatsu H6568), so we will have 14 sixteen channels ADC modules (Lecroy 4300). For timing studies we record TDC information for the trigger counters; we use 2 eight channel TDC modules (Lecroy 2228A). For recording rates we use 4 twelve channel scaler modules (Lecroy 2551).

All these modules fit in one camac crate that is readout by a PC linux trough a Jorway 73A camac crate controller. We use standard NIM logic to obtain the trigger to the camac crate. A SCSI interface ADAPTEC AHA 2940 is used to connect the crate controller to the PC. For camac readout we use library sjyLX available from Fermilab computing division. For online analysis and histograms we use Fermilab’s histoscope package. A detailed description of the daq system is given below.

1. FPD TRIGGER

We need to have the D0 interaction marker clock as an input which we delay to have the early clock and then the early clock gets delayed by 180 ns to get the intime clock (we use delay/gate generators Phillips 794), the 180 ns delay is the average separation for early and intime signals for Q1 and Q2 detectors. We need to synchronize the signals from the scintillation counters to these clocks. The intime and early clocks have a width of 60ns to cover both detectors at quadrupoles Q1 and Q2 (see figure 1). The same clock can also be used for the dipoles, however for the beam test run we wont distinguish online between early and in time hits on the dipoles, the discrimination of early and intime peaks for these detectors will be done by an offline study of their TDC distributions.

The trigger scintillation counter signals from the tunnel get connected to a lemo panel, from that panel we use proper delay cables to synchronize the signals, then we discriminate them (discriminator Lecroy 620BL with outputs 5 ns wide). We use one discriminator module for the 8 quadrupole detectors and a second module is used for the dipole detectors. Two outputs of the quadrupole discriminator are used to feed two different discriminators (Phillips 710) which have a veto input, one discriminator is vetoed with , the other is vetoed with . With those discriminators vetoed in this way we separate early signals from intime signals; the outputs of the vetoed dicriminators are 50 ns wide. All coincidences needed to build the trigger are done with 50ns signals. The third output of the quadrupole discriminator is connected to a fan-out module (Lecroy 4300); one output of the fan-out goes to a gate delay generator (Lecroy 222), the delayed signal is used as the input to the camac TDCs.

For synchronization of the trigger counter signals and the intime clock we first synchronize the clocks to the signal that arrives the latest, after that we add delay cables on the other trigger counter signals at the input panel. To have both Q1 and Q2 detectors timed to the same clock, the intime signal peaks from Q1 and Q2 should be separated by 26 ns after synchronizing (the same for the early signals). This difference in timing is due to the physical separation of the two detectors in the tunnel.

Having the intime and early signals we just build our trigger system. There are four triggers that are obtained by requiring an early hit at one side of the interaction point and an intime hit at the diagonally opposite side (halo triggers):

· EPU.AD = (EP1U+EP2U).A1D.A2D

· EPD.AU = (EP1D+EP2D).A1U.A2U

· EAU.PD = (EA1U+EA2U).P1D.P2D

· EAD.PU = (EA1D+EA2D).P1U.P2U

The early hit requirement is the OR of the two counters defining one arm spectrometer, the intime hit requirement is the coincidence of the two counters of the spectrometer. Once the OR is made, we delay (Phillips 794) the early hit to be in coincidence with the intime clock, the delay time is 180 ns. All the coincidences are obtained using either logic unit Lecroy 365AL or Phillips 755.

We also have two triggers that require intime hits at both diagonally opposite sides (elastic triggers):

· PU.AD = P1U.P2U.A1D.A2D

· PD.AU = P1D.P2D.A1U.A2U

FIGURE 1 : TIMING

Besides the physics triggers, we also have the minimum bias trigger which is the OR of all the intime scintillation counter signals. Up to now we are putting in an OR all the 8 trigger counters in the vertical pots and the two trigger counters from the dipole pots. The minimum bias trigger has to be prescaled, the prescaling factor depends on the trigger rates, a prescaling factor greater than 900 should be safe to avoid writing a lot of data with only one counter firing. The last trigger that we produce is the pedestal trigger, what we use is the intime clock delayed such that we don’t expect any signal from the beam to happen at the time the pedestal trigger fires. We have to have a heavy prescaling factor on the pedestal trigger since it is produced every 396 ns, a prescaling factor of 999x999x10 would produce a pedestal trigger with a frequency of 0.2 HZ and should be appropriate.

All the 8 triggers (halo+elastic+min bias prescaled+pedestal prescaled) are put in an OR to make the MASTER trigger, the master trigger signal is the TDC start for the camac TDCs (we are using Lecroy 2228A TDCS). We also need an ADC gate that has to be produced after the camac busy signal, so the gate is generated by using a trigger output from camac that is produced simultaneously with the busy signal.

To monitor rates online we use scaler displays Jorway 1880B and a preset scaler Jorway 1883B. The preset scaler is setup to count 10000 counts and then gate off all the display scalers. The input to the preset scaler is a pulser that must always be running at 1kHz in that way the preset scaler is just leaving a window in time of 10 secs for the display scalers to count.

Figure 2 shows the circuit diagram for the trigger logic.

FIGURE 2 : TRIGGER LOGIC

2. CAMAC READOUT

Camac readout starts when there is a trigger input to the LAM module RFD02. Once the RFD02 module gets an input trigger, it produces the computer busy signal and also a trigger output. The daq program just waits until it observes a trigger on the LAM module, then it starts reading out. The busy signal is used to veto the module that produces the early clock (this will busy out the whole logic). We also use the signal to put it in coincidence with a pulser, this allows us to count number of seconds that the system was alive to accept triggers, this is important to be able to determine rates in Hz for the camac scalers. The order of the modules in the camac crate is shown in table 1.

The order of the modules on the camac crate and the order of scalers (table 2) and input triggers to the LAM module (table 3) are fixed in the daq program. Changing this order requires some modifications in the daq program that are described in section 3.

TABLE 1: Camac Crate

Slot 1	DATAWAY DISPLAY
Slot 2	LAM RFD02
Slot 3	SCALER MODULE 2551
Slot 4	SCALER MODULE 2551
Slot 5	SCALER MODULE 2551
Slot 6	SCALER MODULE 2551
Slot 7	TDC MODULE 2228A
Slot 8	TDC MODULE 2228A
Slot 9	FERA DRIVER 4301
Slot 10	FERA ADC 4300
Slot 11	FERA ADC 4300
Slot 12	FERA ADC 4300
Slot 13	FERA ADC 4300
Slot 14	FERA ADC 4300
Slot 15	FERA ADC 4300
Slot 16	FERA ADC 4300
Slot 17	FERA ADC 4300
Slot 18	FERA ADC 4300
Slot 19	FERA ADC 4300
Slot 20	FERA ADC 4300
Slot 21	FERA ADC 4300
Slot 22	FERA ADC 4300
Slot 23	FERA ADC 4300
Slot 24	CRATE CONTROLLER J73A
Slot 25	CRATE CONTROLLER J73A

Along with the input triggers to the camac LAM module, we have to provide TDC start signals for each TDC module. We also have to provide the ADC gate to the FERA driver (GAI input), the FERA driver then distributes the gate to all the ADC modules. The TDC start signal is provided by the MASTER trigger obtained from the NIM logic. To have the ADC gate we use the output trigger of the lAM module and use a delay gate generator (Lecroy 222) to be able to modify the delay and width of the gate. The ADC gate delay depends on the arrival of the scintillating fiber detector signals to the fera ADCS. Since we use RG58 cables for the trigger scintillator signals (b=0.68) and ribbon cables for the scintillating fiber detector signals (b=0.78) we have to make as short as possible the RG58 cables and put extra delay on the ribbon cables in that way the arrival of the scintillating fiber signals is later than the camac trigger.

The way the daq program has been setup requires that always a TDC start pulse must be provided. If only the ADC gate is provided with no TDC start pulse, the daq will be reading always zero.

The order of the scalers is shown in table 2, the order of the input triggers to the RFD02 module is shown in table 3.

TABLE 2 : SCALERS

Scaler module 1-slot 3		Scaler module 2 – slot 4		Scaler module 3 – slot 5		Scaler module 4 – slot 6
Channel #	Signal	Channel #	Signal	Channel #	signal	Channel #	Signal
0	P1U EARLY	0	P1U INTIME	0	EPU.AD	0	PED. PR.
1	P1D EARLY	1	P1D INTIME	1	EAU.PD	1	MASTER
2	P2U EARLY	2	P2U INTIME	2	EPD.AU	2
3	P2D EARLY	3	P2D INTIME	3	EAD.PU	3
4	A1U EARLY	4	A1U INTIME	4	AU.PD	4
5	A1D EARLY	5	A1D INTIME	5	AD.PU	5
6	A2U EARLY	6	A2U INTIME	6	M. B. PR.	6
7	A2D EARLY	7	A2D INTIME	7	PULSER	7
8	EP1U.EP2U	8	P1U.P2U	8	GPULSER	8
9	EP1D.EP2D	9	P1D.P2D	9	ADIP1	9
10	EA1U.EA2U	10	A1U.A2U	10	ADIP2	10
11	EA1D.EA2D	11	A1D.A2D	11	ADIP1.ADIP2	11

TABLE 3 : Input triggers to LAM module

Channel #	1	2	3	4	5	6	7	8
Trigger	EPU.AD	EPD.AU	EAU.PD	EAD.PU	AU.PD	AD.PU	M.B. PR.	PED. PR.

3. DAQ PROGRAM

There are three programs that have to be run to get the daq working properly:

1) The pedestal program (/home/peds/peds)

2) The Main daq program (/home/daq/rundaq)

3) The acnet program (/home/acnet/lx/acnet)

One has to run first the pedestal program to obtain the ADC pedestals. This is needed because the ADCS are readout in the mode of zero suppression. The peds program waits until a trigger at input 8 (pedestal prescaled input, see table 3) of the LAM RFD02 module gets a signal, then it reads out the FERA ADC modules and produces a file with all ADC pedestals, the actual time when the peds program was run gets encrypted as part of the pedestal file name, one example is /data/peds/y00m07d26t1546.txt. The file with the pedestal information used for pedestal subtraction is /home/peds/CURRENT_PEDESTALS, to update the file one has to do a logical link to the latest pedestal file produced with program peds ( ln –s /data/peds/y00m07d26t1546.txt /home/peds/CURRENT_PEDESTALS).

After we have updated the pedestal information we can start taking data by running /home/daq/rundaq program. This program requires as an input, from the screen, the run number, i.e., rundaq <run#>, where run# is an integer number. If run# is 0 the daq will readout the data and display it on the PC but will not write anything on disk. If run# is different from 0, the program verifies that no other data have been previously obtained with the same run number. After verification the daq program starts taking data. First it opens the Histogram windows and trigger buttoms. There will be three buttoms, two are to reset histograms and ntuple, the third one is the end of run buttom. There will be a window with histograms for the first 4 ADC channels. There is another window with a histogram for the total number of ADC words readout. One last window is used as the menu for all histograms and the ntuple .

The third program to run is the ACNET program. The purpose of this program is to obtain accelerator parameter information. It uses a beams division package called export that just allows communication between our daq pc and beams division computer. Right now there are 5 lists of accelerator device information. However we still need to update the variables on these lists. The ACNET program runs in parallel to the main daq program.

When program rundaq is started the first steps that are executed are:

1) The program verifies run number

2) Creates three shared memory segments. Two of the segments are used as data buffers A and B, the third segment is used as a status flag.

3) Camac modules are initialized.

4) Logger program (/home/daq/logdaq) is spawned.

When data is being taken three programs are running in parallel: rundaq, logdaq and acnet. The three programs look always at the shared memory status flag. The status flag is a record that contains the run number, run status, buffer A and buffer B status. Program rundaq starts filling out buffer A until the buffer gets full and then sets up the buffer A status to FULL then waits until buffer B is EMPTY and starts filling it out. Program logdaq waits until buffer A status is FULL and proceeds to fill out the histograms and write data to disk, once logdaq has finished with buffer A it sets the buffer status A to EMPTY and waits until the status of buffer B is FULL and then writes the buffer to disk and updates

histograms and then sets the buffer B status to EMPTY. The loop is finished if the run status is set to STOP when the end of run buttom is pressed. The name of the file where data is written to disk is /data/run<run#>.dat.

Program acnet looks at the status flag for run number, if run number is not 0 then acnet starts writing the accelerator data to disk to the file: /data/acnet/run<run#>. Acnet data is being updated with a period of 1 minute.

The size of buffers A and B are set to 400 Kbytes (or 100000 words of 32 bits), this number can be changed by editing the daq contants definition file: /home/daq/daq.h. The linux command ipcs displays the shared memory segments that are created with their corresponding shared memory ids, if the size of the buffers is updated one should also remove the existent shared memory segments, one can do that by using the linux command ipcrm –shm <shm id>.

File /home/daq/daq.h also has information about the order of the modules in the camac crate, if the type of modules or number of modules need to be changed, the file daq.h should be updated properly.

To display histograms and ntuple the Fermilab package histoscope is used. If new histograms are needed, one can just edit the file /home/daq/hist.c and book the histograms. The number of histograms should be maintained to the minimum since filling out too many histograms can produce some deadtime to the data taking.

Standard IEEE camac subroutines are used to read out the camac modules. These subroutines for linux and for crate controller Jorway 73A are found in the library sjyLX. The scalers are 24 bit, TDC data are 16 bit and the ADC data are 16 bit. The ADC data format for zero suppression is shown in table 4, for modules containing channels with non-zero data there will be a header word giving the information about the module number (virtual station number) counting as 0 the closest module to the fera driver. The word count in the header tells the number of channels the ADC module has with non-zero data. If the word count is 0 it means that all 16 channels have data. If all the 16 channels of an ADC module have 0 data, no information for that module would appear at all (not even the header word).

Table 4: ADC DATA FORMAT

BIT #	16	Bits 12 to 15	11	10	9	Bits 1 to 8
Header word	1	Word count= 0 to 15	0	0	0	Virtual station number
First channel with data	0	Sub-address of first channel with data	DATA
Next channel with data	0	Sub-address of second channel with data	DATA
.	0	.	DATA
.	0	.	DATA
Last channel with data	0	Sub-address of last channel with data	DATA

The data buffers are 32 bit. To reduce memory the daq program packs the 16 bit data into 32 bit words. Each data buffer is full of camac information, at the end of the buffer a small record is added giving information about the buffer. Because of this, two types of data events are defined for each buffer: Physics data and end of buffer data. Tables 5 and 6 show formats these two types of data. The way the data should be unpacked can be found in the subroutine /home/daq/hist.c. This subroutine unpacks the camac data to fill out the online histograms. When reading the data from the data file one has to start reading the begin of run record which includes run number, time stamp and comment.

The format of the acnet data can be obtained from the file /home/acnet/src/acnet.c. Since the acnet data is still to be defined no description of that data can be made on this document.