This board will support the level 1 and level 2 SCA buffers, the baseline subtractor circuit and the decision maker. The decision maker compares the output with a reference threshold. The baseline subtractor circuit contains two sample and holds and a low noise differential amplifier with high common-mode rejection ratio.
The Decision Maker Circuit

Sample and Hold and Output Buffer
The output of the level 2 SCA buffer is stored on this sample and hold for digitization. The output buffer provides tri-state output and drives the BLS backplane in a multiplexed fashion.
This motherboard supports the BLS and analog buffering circuitry for 48 channels on a preamp motherboard. The trigger tower signals are scaled to become approximately proportional to transverse energy. This prevents the large energy signals from saturating electronics. The BLS motherboard also contains a 48 bit wide by 46 bit deep memory to hold the individual gains chosen for each of the 48 channel and for up to 46 triggers waiting for a level 2 decision or waiting to be digitized.
One of the three backplanes will be modified by adding 32 more pins to accomodate new control lines and power pins. They are required by the SCAs.
Because of the addition of a high speed filter, a higher degree of integration and a modest increase in the power is needed.
This is a fanout/driver module. It receives all of the signals generated by the timing and control system and remakes them to be used on the BLS crate. The difference is that now it will handle more signals and a slightly tighter timing requirement.