TandC controller board output Buffer Format: (available on every event) Presently 4 long_words Starting at address 0x342000 and length of buffer is given at address 0xFF0082 Word 0 is: bits 0-15 L3 Transfer Number bits 16-23 CSR 0 bits 3-10 3-4 = L1 trig sel 5-6 = Ext trig sel 7 = SCL enabled 8-9 = L2 mode control 10 = Auto L1 accept bits 24-27 Number of events waiting to be digitized when this event started digitization bits 28-31 Number of events waiting for an L2 decision Word 1 is: bits 0-7 L1 Bunch number (0-158 are legal) bits 8-23 L1 Turn number bits 24-29 L1sca Cap address (1-46 are legal) bit 30 L1sca used (0=up, 1=down) bit 31 ==0 (spare) Word 2 is: bits 0-2 CSR 0 bits 11-13 bit 3 CSR 0 bit 0 (master/slave) bit 4 CSR 0 bit 15 (local DanOwen bit) bit 5 L2 error flag bits 6-7 spare bit3 8-13 L2sca Cap address (1-46 are legal) bits 14-15 ==0 (spare) bits 16-23 card address (0-11=T&C, 16=T&C control, 17=SB tester, 18=5K tester) bit 24 SCL error bit 25 SCL SYNCH lost bit 26 Beam period bit 27 cosmic gap bit 28 L1 error flag bits 29-31 ==0 (spare) Word 3 is: bits 0-15 FPGA code version number bits 16-31 reserved There is also a non-volatile Error log/clock buffer starting at address 0x340000 NOT YET functional .....format to be added....... Finally there are 8 16 bit control registers on the T&C Controller board starting at address 0xFF0080 Word 0 is: Read/write, primary control register bit 0 Master/slave bit 1 Controls fixed bunch mode running. 0=default scans thru all valid beam crossings (7,10,...), while 1 over-rides and selects the single bunch selected by word 3 bits 0-7. Valid values are 0 thru 158 which select bunchs 7-158,0-6 respectively. bit 2 computer SCL ack bit 3-4 L1 trig sel 0=Diabale all triggers, 1=SCL L1 accept, 2=random local trigger, 3= bit 5 No Beam 0=in spill peds 1=in gap peds bit 6 EXT trig sel 0=, 1= bit 7 SCL enable bit 8-9 Auto L2 mode 0=wait for L2 accept, 1=, 2=automatic accept 1 in 32, 3= bit 10 Auto L1 accept (local trigger) bit 11 Should be copy of BLS mode bit 7 bit 12-14 Should be copy of BLS mode bits 0-2 bit 15 Local DO bit (when set will turn zero suppression off for any L1 accept associated with cal trig term 0 firing) Word 1 is: Read only, output buffer length A write to this location does a local SCL init. Word 2 is: Read only, status word, bits as follows: bit 0 L1 busy bit 1 L2 busy bit 2 Upper SCA chip busy (waiting readout) bit 3 Lower SCA chip busy (waiting readout) bit 4 L1 fifo NOT empty bit 5 L2 fifo NOT empty bit 6 ADC fifo NOT empty bit 7 sync lost bit 8 Fifo 1 full bit 9 Fifo 2 full bit 10 ADC fifo full bit 11 L1 error bit 12 L2 error bit 13 SCL data error bit 14 SCL link error bit 15 Hold timeout error Word 3 is: Read/Write, secondary control register (Only effects framework AND/OR terms) Should be set to default of 0x00F0. bit 0-5 L1 SCA cell number associated with trigger reguest valid values are 0-41 (Hex 29), which select cells 8-46 of the chip defined by bit 6, or 5-7 of the other chip, respectively. Values 0x2A-2F disable all fixed cell triggers (except when bit 12 is set, see below). values 0x30-3F cause each successive trigger to use the next cell in the SCA selected by bit 6. bit 6 L1 SCA chip select (0=upper, 1=lower) bit 7 when set selects scan mode. If bit 6 =0, then use cell selected by bits 0-5 and cycle upper/lower. If bit 6 = 1, then ignore bits 0-5 and cycle thru all cells, firing pulser and trigger on different cell each event. bit 8-10 controls relative timing of trigger and pulser. 0 == NORMAL timing, 1=pulser early by 1 tick, 2=pulser early by 2 ticks, 3=pulser early by 3 ticks, 4=pulser late by 2 ticks, 5=pulser late by 3 ticks, 6=pulser late by 4 ticks, 7=pulser late by 1 tick bit 11 To Be Defined bit 12 Force fixed cell triggers to only use a single L2 SCA cell if set to one. The L2 SCA cell used is defined by bits 0-5. Valid values are 1-46 (Hex 2E) which selects cells 1-46. Values 0 and 0x2F-0x3F disable all fixed cell triggers. The L1 SCA cell is always fixed at cell 5 of the L1 SCA selected by bit 6, unless bit 7 as set. Then the L1 SCA cell used scans thru all available L1 SCA cells, randomly choosing either the up or the down L1 SCA. bit 13-15 To Be Defined Word 4 is: Read/Write, spare WC register for use with the PIB board Presently defaults to 0x10A, and gets rewritten to that value on every SCL init Word 5 is: ReadOnly, Last L3 transfer number processed, cleared on every SCL init Word 6 is: Read/Write, Defines which of the 16 AND/OR trigger bits also sends a COMMAND to all pulsers to fire. Defaults to all disabled, which means that no commands are ever sent to the pulsers. The definitions of when a given AND/OR term is fired, is still being defined. But for now (As of version 27), the low order 8 bits are different rate triggers synchronized to bunch numbers. Bit 0 is a special low rate trigger. If a trigger is recieved when this bit is set, and the ADC crates are in the correct mode, zero suppression is turned off for this trigger readout only. The approximate rate for the eight bits is: 1/10, 1,11,11,11,22,45, and 90 Hz. Bits 2,3 and and 4 all run at about 11 Hz, but bit 4 has uniform spacing, bit 3 sends 2 triggers in rapid succession, followed but a longer pause to keep the average rate the same. Bit 2 sends a burst of four triggers, followed by an even longer pause to keep the average rate at 11 Hz. The high order 8 bits are different rate triggers synchronized to L1/L2 SCA cell values. How the SCA cells are choosen is set by the bits in the fourth control register (word 3). The firing rate is approximately the same as the low order 8 bits. Word 7 is: ReadOnly, Crate id == 4C --------------------------------------------------------------------------------- For Run II, the BLS mode in the ADC crate controller has changed: 5 bits are now defined: 0-3 and bit 7 The T&C controller needs to know about bits 0-2 and bit 7.....see above word 0 BIT 3 is reserved for "single buffer mode", and should always be set. That allows for up to 16 possible BLS modes: BIT 7 == 0 Single readout mode bits 0-2 = 0 Normal running mode = 1 Do not do BLS subtraction (used to check offset in L1 SCA) = 2 Force X1 readout path = 3 Force X8 readout path = 4 Baseline 1 tick (132ns) earlier = 5 Baseline 2 ticks earlier = 6 To be Defined (defaults to normal running mode) = 7 Check comparator timing (used to ensure auto gain select not marginal) BIT 7 == 1 Multiple readout mode bits 0-2 = 0 Force X1 readout path and baseline 1 tick earlier = 1 Force X8 readout path and baseline 1 tick earlier = 2 Force X1 readout path and baseline 2 ticks earlier = 3 Force X8 readout path and baseline 2 ticks earlier = 4 Dual Readout, both X1 and X8 data = 5 Dual readout, check L1 holding = 6 Dual readout, check L2 holding = 7 Triple readout, sample tree points (used to check beam readout timing)