SCA Design Changes/Evolution

Calorimetery

1998-07-24

The original design from S. Kleinfelder shows the following errors in Magic.

:drc count
Cell cker has 20 error tiles.
Cell hclock has 10 error tiles.
Cell z10 has just one error tile.
:drc why
P-Well spacing must be at least 9 (MOSIS rule #1.2)
Cap must be on a flat surface (MOSIS rule #11.4)

· Looking at the hierarchy below it is seen that 'cker' contains a subcell 'hclock' The correction involves adding P-Well material to the transistor areas. Fixing the 'hclock' cell corrects the 'cker' errors.

HIERARCHY

cal4
  |__ CAL4
        |__ left6
        |     |__ zpadin2
        |     |__ reads
        |     |     |__ read5c
        |     |__ cker
        |           |__ hclock
        |__ channel5
        |     |__ celltop5
        |     |__ cell5s
        |     |     |__ cell5e
        |     |__ reset5
        |     |__ z10
        |     |__ zoutpad5
        |__ right6
              |__ writes
              |     |__ write5c
              |__ zpadin2
              |__ cker
                    |__ hclock

· 'z10' cells have also been corrected. The correction required moving the capacitors away from the P-Well (non-flat) surface.

· There was one pin (OP Amp reference) that had no protection from static damage. Since we are making more units on a 6" wafer line, we will need to have new masks made for the process. It was decided that protection diodes would be implemented on the next design run.

· CIF files were generated with the above fixes and sent to Supertex for fabrication.