DØ Calorimeter Electronics Upgrade Meeting Minutes

September 23, 1999

present:: M. Tuts, D. Huffman, L. Bagby, P. Liston, D. Elvira, L. Groer, B. Olivier, M. Gao; Paris: H. Lebbolo, F. Machefert; SUNY-SB: D. Schamberger

Meeting time is 9:00 am, Thursdays in DAB1. Video connection available.
Contact Leslie Groer groer@fnal.gov.

= ACTION ITEM

Pulser System

HL has the schematics from DH for the front and back panels.
DH has noted a couple of times when the pulser PS did not turn on after a quick power cycle - it might be a matter that the load is not correct. HL wondered if the monitor board could be causing this but DH does not think so. The decision is to put a AC solid-state relay in to be able to cycle the PS remotely. This is a $20 part that FNAL will put in with the rest of the monitoring stuff.
The final PS needs a 3-wire AC input with ground independent of the ground of the PS.
There will be one 7-contact output connector going to a pulser box. DH would like a spare cable that he can test the PS with a made up load. HL will provide DH with the pin assignments.
The final production version of the pulser is being tested with no problems seen so far. They will have 11 boxes next week and 3 more in mid-Oct.
The pulser fanout daughtercards should be here with the rest of the fanouts in Nov. BLS DS reported progress on the daughtercard - should be able to plug in tomorrow. They are missing a few pieces needed to make more cards - trying to track these down. The checkout of the motherboard has begun. MT wondered if we were on schedule for ordering the 5k test stand quantity of daughtercards and motherboards by mid-Oct. This is a little uncertain.
MSU is supposed to be working on the trigger resistors.
The copper grounding straps for the BLS backplanes are being made at Nevis. Should take about 1-2 weeks. They will be sent out for tinning. Should get all 460 pieces. Timing and Control DE has not seen errors so far in the simulation. There needs to be a reset on the RAM memory as it starts in state 3 - this is the timeout signal that the information in the SCA cell is too old to be reliable. DE diconnected the timeout and the FPGA still sticks in this state. DS suggested that the FPGA might reset to all bits ON. There needs to be an initalization to zero. There are some state transitions and priority signal glitches that DE is chasing down. He is working on the reset problems. No time violation problems have been seen so far.
DS will bring T+C module out for Oct 6 collab. meeting. Software BO talking to Jae Yu and Mrinmoy Bhatterjee about the CalExamine processes.
Jae read out a calorimeter crate with the online system in July. The unpacking of the data is not in the correct format for commisioning/electronics debugging though as it comes out in eta-phi format rather than channel, ADC, BLS etc. DS believes that there is a piece of Mike Fortner's offline unpacker that will help. The L3 verison is different.
We need the commissioning examine to reproduce much of the functionality of the bit-3 setup (b3run) in the 5k teststand PC.
DS has found a VMS disk with the old CALELEC software that BO will look at. There is a Rochester student (Florencia Canneli) also working on CalExamine. Preamps BO has been working on pulser patterns at DS's suggestion to ensure that the Run 2 system can emulate the Run 1 patterns.
Zarah has finished with the old preamp boards and running tests in the 5k test stand so the r.h.s. of the box can be filled with new boards. We need to remove old boards, change the PS rails, remove the old rails, put in new wider rails to accommodate thick boards, stuff thick boards. LG and MG will work on this.
LB and LG met with UTY Sept 21. KTY wanted to change test parameters for A (Vpp) and C (fall-time) species. We determined they had been using ES2 data rather than preproduction to determine their windows. It is still not know why there was a difference between ES2 and preproduction. One of the speculations is that different caps were used. KTY's QA department is quibbling. We agreed KTY would pull the first 20 off the A production line and would send us the curves and numbers.
LB has a few things to fix on the H-jig. The PO for the H's is in the system but no buyer yet. Might get placed next week.
MT reported that Metrocircuits is on schedule for motherboard fabrication 1-2 weeks for 1st 600, 1-2 weeks later for next 600. We should have precision resistors by mid-Oct. We need to get bids on the assembly. PL visited the Chipco facility and came away with a good impression.
MG has been working on the database that SF started during the summer. He has three tables in the database - preamps, motherboards and preamp boxes. Power Supplies DH has one loaded monitor board that he is installing. Almost ready to give the go ahead for the production quantity. Will need some technical help for installation when there come in. Don Emory might be available.
DH has conducted more tests of the supply under load. He wants to add a cooling shunt plate under the monitor board which will be soldered to the water manifold. Without this cooling the board goes to 50 deg C. With a thin piece of copper the Vicor temp went a little higher but with a 1/8" plate the Vicor was about 27 deg C and the plate at less than ambient (25 deg C). There will only be a few screws attaching the board.
We have no further information on the BLS PS needs. Once we have a working final BLS (mid-Oct?), the PS in the test stand can be modified to test the load (this one is half modified already). This will probably take a week.
PL reported the PS 3-color front-panels were quoted at $600. The 30 monitor board PO has been signed off but purchasing is swamped. SCAs PL reported the 6" wafer packaging started yesterday. They are still trying to optimize the 4" wafers. They will use 200 more in a test.
The SCA burn-in stand FPGA died again - DH replaced it. Note in the real system DS will drive only 6 SCAs per FPGA instead of 49. Infrastructure MT reported the iron should open Monday and that Pete Simon rework of chilled water might be delayed a bit. ICD LaTech sent LB a fax. The motherboard ground plane has been causing noise. They are relaying out one channel.

This page updated 30-September-1999
Send comments/corrections to Leslie Groer groer@fnal.gov