DØ Calorimeter Electronics Upgrade Meeting Minutes

October 21, 1999

present:: M. Tuts, D. Schamberger, D. Huffman, L. Bagby, P. Liston, D. Elvira, L. Groer, B. Olivier, M. Gao

Meeting time is 9:00 am, Thursdays in DAB1. Video connection available.
Contact Leslie Groer groer@fnal.gov.

= ACTION ITEM

Pulser System

No video connection but Gisele Martin sent a report: The FANOUT mother boards and SWITCH daughter boards are ready now ;
they have been tested and we are packaging them now.
We will send them next week addressed to Dave Huffman and we 'll arrive at
Fnal the 8th of November.
BO working on CalExamine processes. He hoped to have some plots to show but the Run 2 systems were down. Preamps LB has been communicating with Dan Forest at MicroEngineering about the H-species layout. There were still a couple of concerns about the power requirement on R7 which is slightly smaller than R3 but the same resistance value. Also the island trace for R24a+b was discussed but was deemed to probably not be a problem. It was decided to go ahead and produce the 5 preproduction samples for each of Ha-Hg (except He which we have from KTY already). It was stressed that these not be silicon coated and that they should not do the print-fire-trim on the rest of the substrates in case we need to change the layout.
LB and Shua have been trouble shooting the H-jig and making good progress.
KTY acknowledged that the differences they had seen on the I-species was on the risetime, not the falltime as originally stated. There is a 0.6 micosec difference in the falltime and 15 nsec on the risetime (smaller compared to the Blue Book specs). Vpp is 4.5 V which is in specification. The capacitors C3+C5 (as well as C8+C9 possibly) are from a different manufacturer and might be the source of the differences. KTY will send 100 pieces of the I-species for us to examine more closely.
We have some ship dates from KTY - D + E being sent Oct 22 (5,000 + 8,000) and Oct 29 (1,000 + 2,800). After the meeting we learnt A were at KTY and will be sent to FNAL next week (had to push to get them before the ship date of Nov 5!). Still not sure of C production.
LB received 300 bad connectors from KTY - broken legs, unsqueezed, wrong side squeezed, painted on the wrong side, about 100 with xidation which we could get cleaned if need be. Still no word on the rework price. Not clear that we need to get more connectors yet.
LB has been conferring with LaTech about their tests and plots - still some discrepancies with flipped channels and wrong test points used.
MT reported the PO for Chipco to assemble motherboards has gone out. The PO for the Samtec connector rework is helpd up at Columbia - LG and MT are trying to get this through. Samtec has 25k connectors waiting for a PO to start.
Metrocircuits have had problems with the solder mask lifting off areas around the blind vias. They will be shipping about 200 boards today (ed note: 233 boards arrived 10/25).
LG and CH will box and ship the motherboard components to Chipco. Motherboard PC boards will be shipped as we get them and get the capacitance measured.
MG recorded all the previous motherboard pulser-to-ground capacitance measurements in the database. He has also been producing labels for all the parts we have and expect soon. Note that preamps will take about 400 label sheets! He has found that the printer on DAB3 works the best. We might set up the CodeSoft software on a nearby PC. Power Supplies DH reported all the water manifolds have been mounted on the preamp PSs. Front panels are out for painting. PC boards and parts are at Chipco ready to start - just need the PO. Still miscellaneous parts coming in. Need wire (stranded, vinyl) for PS manufacture - could hold up production.
DH working on safety docs.
Bob Jones group is stuffing the readout boards.
DH has started looking at what needs to be done to rework the BLS PS. SCAs SCA tester for the 8000 6" die-up has been set up and Annie will start working on these today. MG will help her. Annie can probably put in about 2 hours + 2 hours overtime most days. They will label only the good chips.
One 4" wafer was being tested in the packaging process again - still being evaluated. The POs that are in should cover any more that are done.
49 4" chips have been burning in for 6 weeks. BLSs DS expects 40 new assembled daughterboards back end of the week. Shapers are being tested at MTI - they are getting only 20% yield. There is possibly a problem with the tester which can be temperature sensitive. They sent some parts for DS to look at. They have about 5k to test and predict about a week delay for shipping (end Oct). DS might need to open up the spec.
DS has 8 more motherboards - they need one wire added. This will give one-half crate worth.
Some parts for production ordered through FNAL in July still not in - need to track down the status of the POs.
Stuffing going on with parts on hand.
DS will be back at FNAL week of Nov 15 - hopes to bring the 1/2 crate out then of motherboards.
LG will supply labelled 4" SCAs for DS to take to SUNYSB.
DS has relaid out the crate controller with LEDs, test points etc. - getting quotes on manufacture.
We need noise measurements on BLS motherboards with daughterboards before can finalize boards.
DS is having trouble getting reasonable quotes for stuffing 700k individual low profile pins - these need to be placed piece by piece.
The Serial Command Line (SCL) link has been fixed and can readout. They are getting the correct crossing but no L3 transfer number yet. It ran for a few hours. Data rate of 1Hz. It needs Don's magic incantation to work and not user friendly or robust yet.
DS is having his EE student convert from separate timing and readout FPGA to one larger FPGA. Needs to be relaid out.
Some VME access modifications need to be made. 3 FIFOs (32-wide x 64-deep bit) will still be kept outside the FPGA due to their size. Timing and Control DE has finished debugging 5 out of 6 command blocks. These are working and synched correctly. There are glitches expected when incorporated in the rest of the system that will still need to be debugged. He is debugging the final (timeout) block which is more complicated (about 30% of the logic).
The addressing can't be fully tested until the full integration which DE hopes to have some time to work on.

This page updated 25-October-1999
Send comments/corrections to Leslie Groer groer@fnal.gov