This chip is very flexible to changes in design, which is very adequate given the instability of the operating scenario.  It has subsystems of a 1.  clock generator, 2.  write address generator, 3.  write address multiplexer, 4.   trigger decision processor, and 5.  timing and control signal generator.

1. The clock generator first duplicates the frequency of the clock and then uses that as the period of the new signal.
2. The write address generator produces write addresses for the SCA1 and SCA2 pipelines.  The two SCAs are written with the same voltages in the overlap range, allowing both the peak and base to be read always from the same SCA chip.  If the second SCA is being written, the writing continues and the output signals indicate that SCA2 is now selected for writing and is the primary recorder.  If SCA2 was not ready at the time the writing continues on the first chip.
3. The write address multiplexer receives the write address and then outputs the selected address to a one address bus.  It then generates the write address strobes.
4. The timing and control signal generator produces the necessary control signals for the readout of the SCA 1/2 chips.  Given that an SCA chip cannot be read and written at the same time, the signal generator checks if the SCA that needs to be read is the one that is currently being written.  If so, the reading is postponed until the pipeline is full; otherwise, the control signals for the reading sequence are generated.  Two read addresses are generated, one for the peak and one for the base.  After the readout occurs, the SCA chip is made available again for writing or reading by enabling the READY signal to the level 1 processor.