The following are the timing and control signals a BLS board needs to operate:

• WGAT 1/2/3:  The voltage coming from the shaper starts to be followed on the rising edge of this control signal.  On its falling edge, the voltage is held on a capacitor.
• RGAT 1/2/3:  The voltage stored in the capacitor associated with the current address is read on the rising edge of this signal.
• W/RADDR 0-5:  Each signal is one out of five bits to generate numbers from 0 to 47.  The number indicates the capacitor to be read next.
• W/RAST 1/2/3:  The address of the capacitor to be written/read first from/to SCA 1/2/3 is latched on the rising edge of this signal.
• WCLK 1/2:  On its rising edge, the capacitor address associated with SCA 1/2 to be written next is incremented by one unit.
• ARST 1/2/3:  Voltage is reset when ARST is high.
• AMUX 1/2/3:  On its rising edge, it connects the voltage from the SCA 1/2/3 output amplifier to the output pin of the SCA 1/2/3 chip.  On its falling edge it disconnects.
• XSL:  If the signal is low, the gain is selected locally with a comaprator.   If it is high, the gain is controlled remotely.
• CLFF:  Clears the flip-flop that stores the comparison used for the gain selection.
• POSCLK:  On the rising edge of this signal, the result of the x1 versus x8 comparison is stored in a flip-flop.
• INH1:  Signal that makes the x1 or x8 voltage (depending on the result of the comparator) available (low) or not available (high) to the following stage, the peak/base selector.
• INH1:  Signal that makes the peak or base voltage available (low) or not available (high) to the following stage, the subtractor.
• CCBIT:  Computor control bit signal.  If XSL is high, then CCBIT overides the result from the comparator and selects low or high gain.