The timing and controls system provides all the information required by the calorimeter readout electronics to function.  It recieves trigger, accelerator, and clock information through the Serial Command Link (SCL), and provides a precision clock signal and a set of timing signals to perform different tasks.  Some basic precision and non-precision lines are setn from the timing and control device to the BLS crates and boards.  Once there, decoding circuitry reconstructs the full set of signals necessary to control the BLS board.

Each BLS motherboard has 48 detector channels.  Each of two SCA daughter boards has analog memory for handling 12 channels.  The two SCA pipelines are written alternatively.  while one is being written, the other is waiting for a level 1 trigger or being read.  One stores information with a low gain amplification and the other stores the high gain signals.

Status

All signals needed to control the Run II BLS boards have been specified, both at the board and the crate level.  This first prototype board for the FPGA is almost complete and will be tested using a test circuit designed for that purpose. The test circuit probides all the necessary input signals to make the FPGA run. It will also have a test cable connection to allow us to drive a single BLS motherboard.   The design of the BLS motherboard is almost complete and the layout will soon start.

   Signals  Timing and Control Design (FPGA Chips)  Block Diagrams(memory.pdf, test_board.pdf)