DØ Calorimeter Improvement in L1 Noise - August 2002
The motivation for this change was noise observed in the L1 calorimeter trigger. Figure 1 shows a scope picture of the output of the two differential driver cables that come from the BLS board into the trigger receiver card (CTFE) in MCH1 before any modifications. The signal represents the sum of electromagnetic (??) cells from four towers that make up a 0.2 x 0.2 trigger tower. The figures shown here are actually taken from a BLS crate in the 5000-channel test stand on DAB1 but are very representative of what happens in the real electronics. The test stand allows the L1 and L2 accepts to be precisely timed.
Figure 1 shows three regions of interest. For scale, the horizontal time units are 100 us and the vertical scale is 20 mV per division (click on the plot to get the postscript file which has better resolution). The data is stored in the L1 switched capacitor arrays (SCA) every 0.132 us which can clearly be seen as the "wriggle" in the region labelled "3" on the plot where the boards switch from the upper L1 SCA to the lower SCA chip (there are 41 buffers in each chip so it takes about 5 us to fill a chip before switching to the next one). When a L1 accept is issued, the data is transfered from the L1 SCA chip to the L2 SCA chip. In the figure, a L1 accept has been issued at the spike labelled "1" which we will take as time 0. If we were to blow up this region (see http://www.pa.msu.edu/hep/d0/ftp/l1/cal_trig/pictures/coupling_cap/ from Dan Edmunds for details of this region) there is a large positive signal of about 10 us in durations, followed by a negative undershoot which lasts about 60-80 us. The positive fluctuation is about 20 mV which represents about 1 GeV of energy in the EM trigger. Note this would be added to a similar spike from the hadronic sections to give a total of about 2 GeV in the total sum. This caused spurious triggers for thresholds below about 2 GeV. Similarly, because of the undershoot, calorimeter triggers need more energy to overcome the lower baseline for the 10-80 usec recovery.
The reason for the spike is that as the data is transfered from the L1 to the L2 SCA the power rails that drive comparator and other logic cicuits on the SCA daughter card are moving slightly. The movement is only of order 0.1 mV per channel, but when these channels are summed for the trigger, the effect is greatly magnified and then amplified by the trigger drivers.
The next noise effect can be seen in the broad band labelled "2" which occurs on the L2 accept and when the data is transfered from the BLS boards to the ADC boards for digitization. In the test stand, the L2 accept comes in about 120 us - this time can vary in the real system based on the TFW. The periodicity in the noise in this region is a reflection of the slight power shifts occuring during the readout of the BLS boards where the first two towers on the upper half of a board are transfered, then the two lower towers and so on for the next board. There are 8 BLS boards per ADC but 16 BLS boards (2 ADC cards worth) share a common backplane and power rails.
The movement of the power rails for the L1 accept were mitigated by the board changes on Aug 28. Figure 2 shows the improved noise characteristics. The 20 mV spike originally at position "1" is now down at ~4 mV. Note that the low level noise effects exhibited in region "3" of Figure 1 have also been reduced greatly.
The next noise issues to be addressed are those caused during the BLS readout after the L2 accept. Dean Schamberger has modified a couple of test BLS cards to prove the proposed fixes will work. The fix consists of replacing a passive resistor pack (8-pin SIP) with an active component which will prevent the change in the power draw when switching from the upper half to the lower half of the BLS board.
Figure 3a and 3b show test boards modified with the active SIP component, (the second uses an external wire to xxxxxxxxxxx which seems to have had little effect).
The active termination seems to have reduced the effect of the L2 accept dramatically. There is still a spike at the beginning of the cycle which is caused by all 12 CMOS chips??? turning on in preparation for driving the data out the backplane to the ADC crates. Note that this spike would require a board redesign to further separate the analg/digital power sources so this will be permanent feature of the trigger input for Run 2.
[I do not recall what you did to improve things for the cap_rework plot.]
As a word of caution, Dean showed that a single bad BLS board in the crate that affects the power rails can have severe consequences on the L1 trigger, even if that board itself does not have any trigger inputs. Figure 5 shows the effects on the trigger input for board xx when board yy was bad.
