DFE | AFE2t Personality

AFEIIt Personality

Introduction

Each AFE board maps up to 512 discriminator bits onto up to four LVDS output links. Each LVDS output link can transmit up to 140 user bits per 132ns crossing. In the original AFE board design a pair of LVDSMUX CPLDs were used to map discriminator and control bits onto the LVDS output links. Once programmed into the CPLDs this mapping could not be changed remotely.

The AFEIIt boards replace the two CPLDs with a much larger FPGA ("DFPGA") and implements the bit selection and mapping via muxes controlled by RAMs. There are four RAMs per DFPGA and each RAM is readable and writable at all times. This is important for verification and also to mask off dead channels dynamically.

Detectors

Discriminator bit mapping files for the DFPGA chips in the following detectors:

• CFT-axial (CFTA)
• CPS-axial (CPSA)
• CPS-stereo (CPSS)

There are almost 500 LVDS cables connecting the AFE boards with the rest of the trigger hardware. To determine what goes where refer to the LVDS Cable Map Page.

Mapping Files

Current Version

Version 1 -- for reference only!