DFE >> RunIIb Upgrade >> DFEA2
As the boards arrive they will be checked to see if any damage has occurred in shipment. We will also check for capacitors installed incorrectly, etc. We will verify that the serial number sticker matches the "hardwired" serial number.
A pair of SLDB transmitters will be installed on the board and the pigtail coaxial cables connected and secured to the board.
The DFEA2 boards will be powered up a minimum of 48 hours prior to platform installation. Three crates (enough for all production boards + spares) are being installed in the Combined Test Stand (CTS) now.
To test the DFEC2 and backplane a whole crate will be populated with DFEA2 boards and powered up. Tests will be performed to insure that backplane communication is reliable and all DFEA2 boards initialize and lock onto the master clock and NRZ control bits.
Other crate tests:
The cable test board will generate LVDS test patterns on all DFEA2 inputs. The DFEA2 will check that the pattern is received with no bit errors. The DFEA2 will then be put into a mode where it will generate a fixed pattern on the output links (LVDS and SLDB) and the cable test board will check for bit errors on these links.
The data integrity tests will use the DFEA2's input and output buffers. We will fill the input buffer with test vectors (real or MC data, it doesn't matter), inject the data into the DFEA2 and capture the output vectors in the output buffer. Then we will read the output buffer and compare it against the expected vectors and note any differences.
To get these input/output data files we can either collect the data from the DFEA2s on the platform (ok), or modify trigsim to format these vectors properly and write it to a file (better).
Norik will be responsible for setting up and maintaining a copy of BU's DSAT test stand here at DZERO.