SVT specifications
(Marvin Johnson, 7 March 1997

SOME DESIGN CONSIDERATIONS FOR THE SILICON VERTEX TRIGGER
(Marvin Johnson)

Parameters defined by other parts of the DØ system:

  1. Input data obtained from the silicon by splitting the optical cable.
    This means that :
    1. Data format is that of the SVX II chip plus port card number.

    2. Data input rate is 53 Mhz

    3. Serial format requires 850 nm receiver and HP Glink chip.

    4. Average readout time is around 7 micro seconds
  2. Level 1 input from fiber trigger is the same as the muon format
    1. 6 tracks per sector

    2. Momentum ordered with highest first

    3. Fiber number of the outer inner barrel

    4. Sign of the track

  3. If L2 fiber data is needed, it will only be available by splitting the optical signal; conditions as in item 1 above.

  4. System will be located on the second floor of MCH (no other space)

  5. Each trigger crate will be a geographic sector and will need to conform to DØ specifications for geographic sectors. This includes communication with the trigger framework for trigger information.

  6. Data transfer to L2 will be by a specification that is now being finalized.

  7. Data transfer to L3 will be via a VBD.

  8. Total processing time must be less than 50 microseconds including data readout from SVX II and formatting for L2 Global.

  9. Although not absolutely required, each trigger board should process a multiple of 4 readout fibers. The port card and VRB both are 4 fiber modules.

  10. Modules must support VME 32.

Some design suggestions (not required)

  1. The optical receiver design is done for the readout board so it could be copied.

  2. preliminary design indicates that cluster finding can be done at 53 Mhz with an FPGA. This would eliminate storing all the data and then processing it. (see DØNote 3168)

  3. it appears to be possible to do all the track fitting in commercial DSP boards.

  4. Selecting data in a fiber road can be done with one FPGA for 4 fibers.

  5. VME 64 can do 30 or more Mbytes/second so it is a good candidate for a bus
Some questions:
  1. How to arrange fiber trigger signals relative to Si signals?
    Silicon is 6 fold symmetric. CFT trigger divided into 80 sectors. The fibers determine the roads so one needs to include all the silicon under a group of fiber roads. Would like to have Si trigger divided into sectors so that sector fits into one crate; at 4 fibers per chip, estimate that about 1 sixth of the total fit into one crate , i.e. fiber trigger has 14 sectors per silicon sector so maximum number of trigger tracks is 96.

  2. How many tracks need to be processed per 4 fiber group? (assume 16 maximum, based on study by Jerry Blazey)

  3. How long does the fitting algorithm take in a fast DSP?

  4. How many hits are in each road? This sets the speed required for VME transfers if one goes in this direction.