Minutes of STT meeting at Stony Brook
(28 July 2000)

People present at meeting:
Hal Evans, Eric Hazen, Ulrich Heintz, John Hobbs, Bill Lee, Jim Linnemann (via video-link), Meenakshi Narain, Chuck Pancake, Wendy Taylor, Shouxiang Wu

Minutes:
(Notes taken by Eric Hazen)

  1. Wu's Talk
    Presented slides on MB update (see motherboard documentation )
    Jim L asked about PCI bus state monitoring. No specific provision on MB.
    ** should add logic analyzer test points **
    Can also use signals via "local control" FPGA to make state information available via VME.

  2. Eric's Talk
    (see LTB/LRB documentation)

  3. Hal's Talk
    (see FRC documentation)
    1. J3 Backplane
      Terminator in slot 5
      So, slots 6, 7, 20 are spare J3-equipped slots
      Jim Linneman points out that some crates will need an FRTC (?) terminator module which occupies (any) slot. Also suggests lots of silkscreen labels on the backplane for probing
      Otherwise, as documented by Hal.
    2. T/R Data Format
      Need to move link trailer to bits 16-31 of last word.
      ** this breaks the STC data format - Meena **

      Endian-ness discussion: Alphas are little-endian.
      Final setting will probably need to be determined empirically!
      (all outside-world interfaces should be switch-able)

      L1CTT data padded to multiples of 4 words.
      Min T/R size: 10 words Max T/R size: 54 words

      First T/R word arrives at STC/TFC logic after about 3.5us

      Errors: missing BoE: (two EoE in a row)
      FRC constructs header with SCL BX number and trailer with error bit set

      missing EoE: (two BoE in a row)
      FRC constructs trailer with error bit set (timing of these is not yet well defined)

      [ Jim Linneman again suggested that LVDS links should be protected scrupulously against missing header/trailer words ]

    3. VME Arbitration
      Equal-priority as described except that VBD won't be triggered if there is an SCL_INIT pending.
    4. L3 Data format
      New features: "source ID" in header identifies which card data comes from. Propose to use "data type" from Level 2 definition.

      Word count is at end. All other details subject so possible change.
      ** sure would be nice to identify event boundaries uniquely **
      ** can we agree across the 3 boards on this ?? **

    5. BM/BC Prototol
      Details not discussed (see note on web). More robust than VRB/VRBC scheme because uses full handshaking.
    6. BC/DB Protocol
      L3_READY - driven by DB (logic board) when data ready
      L3_BUSY - driven by BC during transfer

      DB responsibility is to raise L3_READY, make data available for transfer, and to disconnect after transferring trailer.

    7. Data buffer sizes
      VBD readout occupies PCI-3 until complete (but arbitrator can permit an interruption, while leaving VBD waiting. Need just to stay clear of the 100us (?) VME bus timeout).

      Logic boards must provide sufficient FIFO space for one unbiased event plus a (few) normal events.

      If this buffer gets full, need to (a) raise L1_BUSY and (b) dump data. SCL_INIT is to be avoided.

    8. Monitoring
      FRC gets monitor request in L1_QUAL... passes on to other cards.

      Logic boards signal to FRC that monitoring data is ready implicitly by processing and transferring L3 data as usual, then set mon_done[i] register for CPU to notice.

      FRC interrupts CPU, which checks mon_done[], reads data, etc.

      Jim L points out that the read/clear model breaks if a monitor readout cycle is missed. He prefers not clearing anything and letting the CPU handle rollovers. It seems to me that the February review told us to use the read/clear model, but opinions differ...

      Hal's flowchart assumes that monitoring is done is one atomic set of accesses to the VME bus. It was suggested that it be possible to break the accesses up and permit a VBD transfer in the middle. Hal agrees to look at this.

      "End-of-run" monitor request comes only when the system is completely quiet according to Jim L, but he will look into this.

      3 types of monitoring:

      1. COLLECT_STATUS event marked
      2. CPU initiated monitoring (end of run when system is quiet)
      3. diagnostic monitoring (when something breaks; "core dump").

      ** "live" plus buffered monitoring registers should both be PCI-accessible for diagnostic purposes **
      ** LRB needs copy of COLLECT_STATUS in the trailer (or header) to tell it to copy its monitoring registers.

    9. SCL Init
      FRC interrupts CPU. CPU sets scl_ready[i] in all boards. Boards set scl_done[i] when done.
      DB can cause SCL_INIT by pulling L1_ERROR on J3.
    10. FRC/BC Power Estimates
      5W for FRC logic board, 7W for BC PMC board
    11. Status and Plans
      Some logic design done. FPGA coding started in a few cases. Obviously somewhat behind schedule.

  4. Meena's Talk
    (see Meena's transparencies and STC documentation)

  5. John's Talk
    (see John's transparencies and TFC documentation)

  6. Bill Lee's Talk