Agenda:

• status reports []
  • simulator, CPU purchase, STC VHDL code,
• software

Minutes:

1. status reports
   
   • Beam monitoring news [Yi Dai] Yi Dai explained the data flow in the DAQ system, and in particular to the Examine jobs.
     (transparency about DØ data flow: ppt -- pdf)
     He also showed details about the data flow to and from the Vertex-Examine.
     (transparency about data flow for beam monitoring: ppt -- pdf)
     

   • simulator [Silvia Tentindo-Repond]
     A mistake in the KUMAC for the plots and table shown by Silvia last meeting has been corrected -- a corrected version of table shown in meeting of Oct 27 is given below:

     ____________________________________________________________________________
     
        SAMPLE     CFT track/evt    CFTtrks/crate    CFT tracks/   CFT tracks/ 
                                                       sector    sector + overlays  
     	        MV, RMS         MV. RMS        tot entries    tot entries       
     
     ___________________________________________________________________________
         
     
         tt 0mb     36.8+-14.4       10.8+-8.1        589             857
     
         tt 1.1av   40.1+-15.0       11.4+-6.4        483             663
     
         tt 4 mb    51.1+-21.0       17.8+-13.0       718            1122
     
     
       QCD4080 0mb  9.6+-4.1         4.5+-3.3         116             193
     
       QCD4080 2mb  11.1+-5.3        4.9+-3.7         178             248
     
     
     _________________________________________________________________________
     

   • CPU purchase, STT crates [Bill Lee]
     All of the STT crates are now in Jerry Blazey's spreadsheet, so we can keep track of them even though they are not in their final locations.

   • STC VHDL code [Horst Wahl]:
     Both Shweta Lolage at FSU and Alexandre Zabi at BU are working on porting Shweta's and Reginald's STC code into new chip family: Shweta into Altera Apex (software Altera Quartus), and Alexandre into Xilinx (software Xilinx Foundation). From her studies, Shweta concludes that three STC channels (excluding the LUT for CFT to SMT translation) could fit into one Altera EP20K1500E chip of the Altera Apex20KE family. Transparencies from a report given by Shweta last Tuesday (7 Nov.) are available in MSWord and pdf format.
     From porting the stripreader part of the VHDL code into Xilinx, Alexandre Zabi finds that use of resources in a Xilinx chip of comparable size to the Altera Flex10k chip is more economical in Xilinx.