Agenda:

1. FRC design, control data format, event buffer control [Hal Evans]
2. STC design, clustering, hit filter [Bill Earle, Roberto Brown]
3. timing for track fitting in FPGA [Wendy Taylor]
4. look-up method for track fitting [John Hobbs]
5. Use of DFE board for FRC [Hal Evans]
6. Use of DFE board for TFC [John Hobbs]
7. Use of DFE board for STC [Ulrich Heintz]
8. strawman design using common mother board [Eric Hazen]
9. VTM [Ed Barsotti, Bill Hanes]
10. discussion on conceptual design
11. design and production schedule [Eric Hazen, Ulrich Heintz]
12. engineering meeting schedule
13. truncation studies [Maurice Leutenegger]
14. CTT broadcasting, sector overlap [Brian Connolly]
15. queueing studies [Stephan Linn]
16. trigger simulation status, monitoring [Sailesh Chopra]

People present at meeting:
Ed Barsotti (part-time), Fred Borcherding, Roberto Brown (via video-link), Brian Connolly, Bill Earle, Bill Hanes (part-time), Hal Evans, Eric Hazen, Ulrich Heintz, John Hobbs (via video-link), Marvin Johnson, Maurice Leutenegger, Stephan Linn, Manuel Martin, Jamieson Olson, Chuck Pancake (via video-link), Wendy Taylor, Horst Wahl

Minutes:

1. FRC design, control data format, event buffer control [Hal Evans]
   (For slides, see here (pdf) and here (ppt)).
   crossing number comes in twice -- in L1CTT header, and via SCL -- could check it
   Road broadcast - 40 bits wide?
   SCL header is 40 bits
   Track info is 32 bits +track no.
   SCL information to all cards -- included into header
   "SCL init" can happen any 132ns period
   Buffer control done by FRC, independently for each crate;
   buffer management commands sent to all cards in STT (e.g. "write info to buffer #x" )
   

2. STC design, clustering, hit filter [Bill Earle, Roberto Brown]
   • For Bill's slides, see here
   • (For details, see writeups:
     • State machine for input of VTM data: ps, pdf
     • Flow chart for centroid finder: ps, pdf
     • centroid calculation: ps, pdf
     • hit filter: ps, pdf)
   • clusterfinder:
     Bill presented conceptual design of cluster finder algorithm which looks at five strips and determines centroid by calculating delta_x with respect to second of the five strips (makes computation simpler).
     Clusters can go across chip boundaries.
     Comments/questions:
     Marvin: would two hits with zero between them become two clusters or one?
     Answer: one, with centroid between the two.
     -- not clear that this is what we want.
     Fred: can algorithm cope with read-out in nearest neighbor mode? (note that pulseheight could become negative in nearest neighbor mode)
     Meena: This is only first approximation -- refinements will be added later.
     Marvin: Why not use small LUT in conjunction with Newton-Raphson method for division?
     Answer: This possibility has been considered -- see write-up.
     
   • hitfilter:
     presented scheme only for 32 tracks -- Hal pointed out that 46 tracks are foreseen;
     Marvin points out that comparison for hit in road can be done by bitwise comparator -- no need for adder;
     
   • implementation in VHDL:
     Roberto's questions deemed too detailed -- suggest telephone conversations between him and Bill Earle.

3. timing for track fitting in FPGA [Wendy Taylor]
   • (For Wendy's slides, see here (ppt)).
     
   • Original design of track fitting code fully implemented in Altera (using AHDL and graphical input);
   • fits on Flex10K200 (77% of resources utilized);
   • static road 3 algorithm takes 160mus;
   • part of slow-down due to slower clock speed (25MHz instead of 40)
   • try to optimize, reduce number of operations;
   • get ideas from Fred B.?

4. look-up method for track fitting [John Hobbs]
   • (For transparencies, see here)
   • Problem is size of LUT;
   • study possibility of using reduced LUT (using super-road that is good enough for several roads (H-layer offsets),
     and then apply correction to impact parameter depending on real H-layer hit pos.
   • can one do a look-up to obtain track parameters directly? (avoid chisqu. calculation) (but cannot get refined pt measurement this way)
   • If SMT efficiency high, could consider using only inner sublayer;
   • leaning towards using FPGA, but not yet decided.

5. Design options, use of DFE for STC[Ulrich Heintz]
   Use of L1 DFE boards cheaper, reduced engineering? -- not obvious;
   not clear that board space sufficient for STC;
   lack of full VME a disadvantage for L3 read-out.

6. Use of DFE board for FRC [Hal Evans]
   (For slides, see here (pdf), and here (ppt)).
   FRC could live with use of L1DFE boards;
   could have one large daughtercard, but would need outside SLC to LVDS converter.

7. Use of DFE board for TFC [John Hobbs]
   concerns:
   
   size of daughterboard -- not big enough?
   
   would prefer full VME
   
   download of beam position possible? (Fred: yes is possible via 1553 bus)
   
   output to L2CTT via Cypress link

   strawman design using common mother board [Eric Hazen]
   (For Eric's slides see here.)
   For details, see write-up.)
   Proposal is to use common motherboard for all of STT, specifically designed for the purpose;
   motherboard is 9Ux400mm VIPA board, with VIPAJ0, VMEJ1, VMEJ2 and non-std. J3 connectors at back;
   at front has up to five PC-MCI daughtercards (47mmx99mm) to serve as receivers or transmitters;
   one of them is SCL receiver, others could be hot-link, G-link, LVDS channel-link,.. transmitters or receivers
   allows for up to four mezzanine boards (74mm x 249mm) (area of mezzanine cards could also b ecombined to give larger mezzanine cards);
   use VTM for fiber input -- no Glink to LVDS converter required;
   SCL receiver card being designed (PC-MI) daughter card);
   need only 32 bit VME -- could put some P to P links on back;
   need input from FRC, TFC to specify requirements.

   VTM [Ed Barsotti, Bill Hanes]
   

   design and production schedule [Eric Hazen, Ulrich Heintz]
   Eric and Uli have prepared preliminary schedule (Microsoft Project)
   (see here for mpp, pdf.)
   preliminary schedule foresees completion by mid 2001;
   need real input from STT group members to fine-tune;
   need complete tasklist -- Horst, Hal, others.. to send info. to Eric
   need more realistic schedule by mid September.

   discussion on conceptual design
   In general, positive reaction to STT motherboard proposal;
   can J0, J1, J2 run at 26MHz?
   not clear that J3 backplane can be used for road broadcasting
   (Hal Evans quotes Bill Sippach "recoiling in horror" from use of std VME for road broadcasting);
   decision: pursue custom 9U STT-specific motherboard
   BU offers to engineer the motherboard; design will be influenced by L1DFE (get artwork?), as well as similar board being designed for CMS.
   

   engineering meeting schedule
   next STT engineering meeting at Nevis, 24 September

   truncation studies [Maurice Leutenegger]
   

   CTT broadcasting, sector overlap [Brian Connolly]
   

   queueing studies [Stephan Linn]
   (see here for write-up (DØ note 3673, Stephan Linn's first Ptolemy studies)
   Stephan gave a "proof of existence" status report; thinks that Ptolemy is sufficiently general and easy to use to allow detailed queueing simulation of STT;
   presently implemented model is first iteration -- need input to refine model.

   trigger simulation status, monitoring [Sailesh Chopra]
   presentation cancelled since Sailesh had to go to India for personal reasons.

Action items:

• Channel-Link BERT test (ESH)
  (Jamies. O, Fred B not planning this)
• Finalize order for 73 VTMs (UH)
• Make task list and circulate (ESH)
• Get D0 mgt input on WBS, MS-proj (UH)
• Add software, monitoring tasks
• Add realistic scheduling info (ALL)
• Coordinate crate/rack specs with Maryland (ESH)
• Check compatibility of FRC with SVX backplane (ESH, HE)

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last updated 19 August 1999