Meeting of 30 October 1997
8:00 in the Ninth Circle
Agenda:

• Status of single top studies [Terry Heuring]
• some design issues [Uli Heintz]
• information flow to and from SVTpp;
  how many and what tracks do we want from CFT?
• AoB

People present at meeting:
Uli Heintz, Terry Heuring, John Hobbs, Marvin Johnson, Dan Karmgard, Ron Lipton, Meenakshi Narain, Doug Norman, Frédéric Stichelbaut, Horst Wahl, Andrzej Zieminski, Armand Zylberstejn (via video-link)

MINUTES OF MEETING:

1. Status of single top studies [Terry Heuring]
   • Use events generated by Comphep and GEANT Feb 97, latest trigger ntuple maker;
   • compare standard L2 triggers with SVT trigger (impact parameter significance)
   • find:
     e channel: no apparent benefit
     mu channel: maybe net improvement from SVT when compared with MUMAX trigger (with loose moun)
     hadronic channels: to be done
   • note: use of ``medium muon'' in trigger may improve rejection, with little loss in efficiency (pointed out by Frédéric) -- to be checked.
     
   • Terry's transparencies can be found here

2. Design issues [Uli Heintz]
   • Si detector data:
     maybe necessary to do pedestal correction and gain correction of SVX2 data
     at same time as Gray to binary conversion?
   • CFT information (answers to these questions needed for CFT trigger design):
     • mapping of CFT sectors (80 x 4.5 degrees) to SVD sectors (24 x 15 degrees)
     • what information needed for each CFT track
       • presently foreseen: inner/outer fiber ID (11 bits)
       • could give 12, maybe 16 bits
       • use add'l bits for improvements in pt resolution or precison of roads?
     • translation of CFT track information into SVD strip ranges (roads)
   • cluster centroid algorithm
   • track fitting in DSP
     • define linearized fit equations
     • timing?
   Cluster centroid algorithm
   
   
   • need to complete computation in 2 clock cycles (38ns) to avoid having to store data
   • division is time consuming
     DØ  note 3168 (Johnson + Angstadt): (8bit/3bit) in LUT is OK
     (uses 80% RAM on Altera 10k50 FPGA chip)
     DØ  note 3209 (piekarz) (6bit/6bit) needs 112 ns
   • avoid division
   possible scenario:
   • limit cluster to 5 strips, center strip has max. pulse
     
     
   • need to know to m precision, i.e. 1/4 strip pitch;
   • compute
     
     
   • compare
     
   • compute
     (10 bits for , 8 bits for , 2 bits for )
   • to be done:
     MC simulation to check resolution is adequate
     Altera simulation to check timing

3. Design plans [Marvin Johnson]
   (from message received from Marvin after the meeting:)
   Marvin has not had a lot of time to devote to the SVTpp design, but, with some help from Uli and Meena, expects to make some real progress.

   There is some effort to take the L1 concentrator off of the VLPC crates and move them to a totally independent crate. This crate could then do the sorting so that all roads for a given STT region (15 degrees?) would be sent to that processor. This would eliminate cracks and avoid the need for more than 1 line to card. Presumably there would be some address mapper in this receiver board that would take the track label and produce the chip and channel range for all the HDI's. This would then be sent out over a bus to each receiver card.

   All the front end cluster finding etc. can be done with a variation of the VBD. After selecting the roads, the data would be sent to a DSP. It looks reasonable to start specifying the design for each board. Marvin will will work on this during his trip to IEEE.