Minutes of STT meeting 17 April 1998
====================================
 in the Far Side, 9:00 to 11:00

Agenda:
     * STT review postmortem (assuming it is post..)
     * any progress in understanding of performance comparison?
         (STT baseline vs SLIC/FIC/etc.)
     * preparations for L2 workshop
     * AoB

People present at meeting:
Jerry Blazey, Mike Fortner, Phil Gutierrez, Ulrich Heintz, Terry Heuring,
John Hobbs, Jim Linnemann, Meenakshi Narain, Frederic Stichelbaut, Horst Wahl.
(Hal Evans attempt to participate via video-link failed  for reasons beyond
our and his control)

(1) STT review postmortem:
  -- did not take place since we haven't received the review panel report yet;
 but there is word of mouth that the concluison of the review panel is
 positive.
We proceed under the assumption that there is a decision to go ahead.

(2) progress in understanding of performance comparison:
  *  Very little progress since last week's special meeting -- not enough time
     to do homework  (except Mike Fortner).
  *  need to reconstruct "homework list"
  * need to define list of criteria for decision between options

(3) Requirements for STTpp (Ulrich Heintz)
    -------------------------------------
  * Uli presented the list of requirements for the STTpp that had been
    prepared for the special STT meeting on April 7.

  * Points raised during discussion:
     -  number of Glinks per card: is four the limit?
                 people in Saclay say six possible, but not more  (??)
         need to know error rate vs number of inputs per unit area --
           need to define criterion: permissible error rate
                   (1/10^14 bits or 1/10^15 bits ??)     
     - benefit of z_v at L2 time??
         trigger on E_t (jet, e):
          at L2 dominated by error on energy (jets, e), so benefit
          questionable
         trigger on missE_t, SumE_t:
              benefit not known -- needs to be studied;
              Meena will implement z_v finding code in trigger n-tuple code
                => will be possible to do these studies

     - item to be added to list of requirements/criteria:
          - performance at TeV33 conditions -- effect on transfer rate,
               deadtime, ....

     - L2 criterion for acceptale preprocessor performance:
         overall deadtime smaller than 5% at 10kHz L1 accept rate,
             ignoring SVX deadtime
             

(4) Conceptual design for SLIC "standalone" (presented by Mike Fortner):
    --------------------------------------------------------------------

  * conceptual design of "stand-alone" SLIC:
     "stand-alone" = as it would be if it were to be used only for the muon
                     trigger
  * figure of layout can be found at
     http://www.physics.niu.edu/~fortner/d0/trig/slic/SLIC_ALONE.PS
     (note this is layout as perceived by Mike Fortner, based on telephone
     conversation with Al Gara)
  * description  of SLIC:
     - input: 16 Cypress serial links (212MHz)
           (SCL is one of the inputs)
     - every input has serial to parallel conversion 1 --> 8 bits
     - two CPLD's (Complex programmable logic devices) collect 4 bytes
          from one input,
          hand on 32 data bits + 3 address bits + 1 data valid bit
              to 3 CPLD's
     - CPLD's:
        - one sends unbiased input to FIFO in front of "Master DSP"
        - two select words, send to FIFO in front of specific worker DSP's
     - total of four worker DSP's each  of which is split in 2 halves with
           a  processor each
          (but processors in the two halves not completely independent --
               there is some synchronization between them)
          - DSP's have access to SRAM (8 Mbyte)          
          - DSP's have transceiver connection to Master DSP to send 
               their output to Master DSP
      - Master DSP receives unbiased input and DSP output,
          sends data to DPM (dual port memory),
          connected to MBT via FIFO and Cy links,
               and to VME bus via CPLD's

  * discussion of suitability for STT track fitting:
      - SLIC computing power designed so that muon system can handle rate
         which saturates front-end
         (i.e. is overdesigned in processing power, by factor 3 to 6 (?))
      - comparison with STT:
           - muon system has about factor 10 fewer hitclusters
              than STT has to deal with;
           - muon system has total of 160 processors
           - present STT baseline design has 192 processors
               --- is this enough???
      - could one add more DSP's on SLIC?
         - might have to cut SLIC in two to make room for add'l DSP's
             - where to cut?
                before 1st level of CPLD's?
                after 1st level of CPLD's?
      SRAM needs of STT processor card:
            John Hobbs estimates need is 10Mbytes for LUT

(5)  Preparations for L2 workshop:
     -----------------------------
   Things that need to be done:
       * improve our understanding of various options for STT implementation
         - study Jim Linnemann's mammoth list of options, etc., and try to
              assess their performance potential
              -- how well they do the job we want to get done
                                                             [everybody]
     * do cost and engineering manpower comparison of various options
                                                             [Hal Evans,..]
     * continue track fitting implementation studies         [John Hobbs]
     * do more realistic timing studies (RESQ)               [Terry Heuring]
     * think about criteria to be used in deciding between options
                                                             [everybody]