STT meeting
 ===========
     Thursday, 13 May 1999, 13:00 to 14:00
          in the Ninth Circle

Agenda:
  * meeting with NSF/DOE
  * status/progress
       - RESQ
       - track fitting
       - clusterfinding
  * Boston meeting
  * plans for D0 workshop
  * AoB


  
People present at Meeting:
==========================
Sailesh Chopra, Brian Connolly, 
John Hobbs, Stephan Linn, Meenakshi Narain, Wendy Taylor, 
Silvia Tentindo-Repond,  Horst Wahl. 

1. meeting with NSF/DOE 
-----------------------
 There will be a meeting with Alexander Firestone on Friday, 14 May, to discuus
 status of NSF-MRI proposal.
 Transparencies with schedule and cost information have been prepared, to be
 shown if needed.

2. progress:
------------
        
* trigger rate studies (John Hobbs)
   -- expect to be finished soon (2 to 4 weeks)
   
* track fitting in DSP's (John Hobbs):
    Rod Engelmann and student at Stony Brook have implemented static road code
    on new TI floating point DSP; find that time needed is about  16
    microseconds, compatible with  previous estimate (14 microseconds) 
    obtained from emulation of floating point device on an integer device.
    
* track fitting in Altera FPGA (John, Wendy)  
    - code being implemented in Flex10k100; 
    - earlier indications that chip not big enough, but this remedied by 
         code optimization
    - new studies by John seem to indicate that using integer arithmetic 
        may be possible by appropriate approximations in covariance matrix; 
	to be pursued further.
	
* track fitting algorithm (John)
    - best algorithm appears to be a combination of static road algorithm, 
       with second iteration when chisq > 3, discarding "bad" layer
       (this is algorithm that has been used in physics studies);
    - "all-combination" algorithm turns out not to be the best algorithm --
       picks wrong track in many cases.
         	
* FPGA code in STC (Horst, discussion)
  schedules prepared for NSF discussion uncover need for FPGA code to be ready
  very soon: according to BU engineers, STC board lay-out cannot begin before 
  pin-outs are defined, which in turn requires FPGA code to be done.  
  According to them, there is a danger that defining pin-outs before code is 
  finalized may make code inefficient.
  Tasks of the FPGA code on the trigger card are the following:
   - receive SMT information, identify it
   - remove noisy channels
   - do pedestal and gain corrections
   - find clusters
   - determine centroid
   - buffer for output to L3
   - filter clusters (select those in CTT roads), buffer for output to
           track fitter card
   - ...
   - provide monitoring information
   - allow for downloading of constants, LUT's,....
   -....
 
   
  We have to define the cluster algorithm very soon; should be simple -- not all
  cases can be considered at trigger level -- must make sure to cater to 99% of
  cases rather than concentrate on rare pathological cases.
  
  Silvia: first approximation to cluster algorithm exists (see note 
     at http://www-d0.fnal.gov/~wahl/sttdesign/cluster/str_990303.txt)
  
3. Boston meeting:
------------------

  Dorm rooms have been reserved; Jim Linnemann decided also to come to the
  meeting. Agenda to be defined -- Meenakshi welcomes input.
  
4. D0 workshop:
---------------

   Contrary to original indications, triggering will be one of the important
   themes of the Seattle meeting. We have to define our goals for the workshop.
   Harry Weerts wants to know whether we should foresee discussion of alternate
   scenarios in case of non-funding.