Summary of special STT meeting ============================== Tuesday, 13 July 1999, 13:00 to 15:00 in the Ninth Circle Agenda: * DFE option for STT People present at Meeting: ========================== Fred Borcherding, Brian Connolly, Hal Evans (via speaker-phone), John Hobbs (via video-link), Jim Linnemann, Manuel Martin, Chuck Pancake (via video-link), Wendy Taylor, Silvia Tentindo-Repond, Horst Wahl. 1. Conceptual design of L2STT using L1 DFE boards: -------------------------------------------------- Fred Borcherding (interrupted by many questions and discussions) gave a presentation of the conceptual plan for the L2STT using L1 front end boards, and daughter boards customized for the needs of the STT. (see the document available on the Web at http://d0server1.fnal.gov/Www/Stt/dfe/stt_dfe_713.doc). DFE motherboard: ---------------- The DFE motherboard (6U high) has 10 inputs on LVDS link, with high band width ( 53MHz, 28 bit ), and 4 independent output busses; output busses are transmitted to outside world via a transmission module over LVDS or G-link; maximum number of output links is six. In addition to these fast links, there is also a VME (A16 D8) interface to be used for downloading. This VME link also allows reading but at much slower rate. There is also a slow (1MHz) bidirectional 1553 bus which allows boards in a crate to communicate with each other; it can be used for monitoring. The bandwidth of the LVDS links seems adequate, even after allowing for additional overhead due to error correction (which brings bit error rate down to 10^-23). The specific functionality of the boards is defined in the daughterboards and in the firmware implemented in the FPGA's. There can be two daughterboards, or one, depending on the requirements. Manuel and Fred estimate that the larger single daughterboard could accommodate up to 6 large FPGA's (e.g. Altera 20k400), plus RAM and buffers. John asks if modification of motherboard to allow for "full" VME would be possible. Jamieson Olson has said that this would be a radical change, and Fred concurs with this. Alos not obvious that it is really needed. G-link to LVDS conversion: -------------------------- This needs to be engineered. VTM modules have only 4 G-links per module, while in this option, 9 G-links are needed per STC. Questions is how dense these translators can be packed. Pat Sheehan has been thinking about LVDS to G-link conversion, could invest some time thinking about the inverse operation. Marvin suggests to put G-link to LVDS converters on the wall in the moving counting house, next to the optical splitters. This way, no rack space would be used up, and also the density need not be so high. Some of the engineering that went into the VTM could be reused. Note that there is a length limitation of 10m on LVDS links, so STT crates cannot be farther than that from the splitters/converters. FRC: ---- There will be up to 46 roads per 60deg. sector. FRC attaches track ID to roads and sends all roads to all STC cards in the sector. Need SCL (AMCC 16 bits) to LVDS converter (either on FRC or on separate board) -- to be engineered. Jim points out that there may be need for Cypress to LVDS conversion (Cypress link needed for additional L2 "qualifier" information). Manuel thinks that transmsiion of this information can be accommodated within the communication protocol. STC daughterboard: ------------------ would have large FIFO (big enough to accommodate data from one event -- ~1200 deep?) at input (for both SMT and CTT information), to accommodate different clock speeds and also to make sure that CTT roads are available before clusters arrive in window comparators for hit-filtering (Note that CTT road information is guaranteed (by Manuel) to arrive at FRC at most 2.8 musec after L1 accept; SMT information begins to arrive after end of digitization, 3musec after L1 accept). STC board would also need RAM for pedestal information. SMT information arrives in Gray code -- Gray code conversion could be done at same time as pedestal subtraction. STC card also must have buffers (16 events deep) for clusters to be sent to L3 (on L2 accept). Hit filter on STC (based on 46 window comparators) sends clusters in road to TFC. TFC daughterboard: ------------------ TFC needs L2 input buffer for road and cluster information, FPGA's for track finding/fitting, RAM for LUT (translation into physical coordinates, matrix inversion), output buffer(?). TFC has to merge multiple copies of same road with clusters in different layers into one track candidate. Redesign and optimization of track finding and fitting algorithm is in progress (Wendy Taylor). Also Fred and Marvin have ideas about alternate algorithms. John is worried that TFC in this scheme is smaller than previously, with same workload. Wonders whether modification of mother board to make it 9U would be feasible. Marvin thinks that this should not be too difficult. Question: how many tracks per FPGA possible? Jim Linnemann's objections: * yes, save some engineering by use of DFE boards, but instead have to design a whole bunch of other boards -- not obvious thta there is really a net gain. * use of new G-link to LVDS converters means waste of engineering that went into VTM * use of L1 DFE boards makes it even less resembling L2 than present conceptual design * not clear how to accommodate Cypress link which is needed for L2 qualifiers Summary of pro's and con's -------------------------- Advantages: (1) use of the DFE-motherboards means that - input-output handling is taken care of - data flow protocol is well-defined, including facilities for error correction on LVDS link -> very low bit error rate (10^-23) - during normal operation all communication between boards is via point-to-point connections (LVDS or Glink) - no bus - VME bus for downloading is available - 1553 bus for board-to-board communication available, can be used for monitoring - specific functionality is defined by the daughterboards which have large FPGA's on them, plus whatever other hardware is needed to do the particular job (memories, buffers, ..). Therefore, the engineering effort is reduced to - the design/modification of daughterboards (modifying the design of daughterboards foreseen for the L1CTT and broadcasting application) - interface (translator) cards for conversion of Glink to LVDS SCL to LVDS (2) The trigger might be ready for the start of Run II. It would surely be ready before the present nominal design. (3) According to Marvin, it would be appreciably cheaper -> would have enough money for ZVP (4) Same motherboard for L1CTT and STT facilitates maintenance (5) It appears to have the same performance as the baseline conceptual design. Disadvantages: (1) Possible time loss of DFE option is considered and rejected, (2) Some engineering effort already done (e.g. VTM) may be lost. (3) Design of G-link to LVDS converters -- may be difficult; may need a lot of space? (4) Redefining/reshuffling of effort, compared to what is laid out in the MRI proposal. (5)