Documents about STTpp design
Documents about DØ trigger
motherboard, LTB, LRB
(very preliminary)
L1CTT, L1 broadcasting
clustering, STC
Track fitting
STT testing and commissioning:
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STT monitoring:
downloading, control
STT simulator:
Queueing studies:
Links to DØ online related pages:
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Links to DØ electronics related pages:
SMT/STT numbering, data flow, etc.
SMT alignment issues
Links to trigger related pages
VBD,VRB,VTM,...
FPGA's
ps,
pdf
eps,
ps,
pdf,
gif,
jpg
(some versions of WebBrowsers cannot handle this page!)
Links from Manuel's page:
(has links to CFT/CTT related documents)
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(links to information about D0 control system, EPICS, Python, VxWorks)
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(serial link receiver, J3 backplane, D0 trigger system specifications,..)
addendum to DØ note
3599 (more about input data (Silvia, 25 March 1999))
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(note that this page apparently causes Netscape 4.7x on Linux to crash, while Mozilla and Konqueror can handle it; Netscape 4.7 and 6 on Windows is OK)
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Altera Devices
Altera Flex
Altera Acex
Altera Apex
Altera University Program
Xilinx Virtex series
Xilinx University Program
Xilinx University Resource Center
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