Addendum to D0Note3599 STR,24-March-1999 As mentioned in D0Note2599 " THE INPUT DATA FLOW TO L2STT TRIGGER CARD FROM SMT FRONT-END", the SMT data will be provided to the Trigger Card of STT by the VTM Module, in the form of 16 bit words ( see par. XI). Here we want to specify this statement more in detail. There are four copper cables coming out of VTM, there are 4 cables in input as well. Each of these output cables transmits the information coming from two HDIs at once. So in one 16 bit word there will be one 8bit word belonging to HDI 1 (f.ex.) and one 8bit word belonging to HDI 2 ,side by side. See drawing: bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 __________________________________________________ | | | | | | | | || | | | | | | | | -------------------------------------------------- | SEQUENCER ID || SEQUENCER ID | |_______________________||_______________________| | | HDI ID || | HDI ID | |______________|________||______________|________| | 1| 0| CHIP ID || 1| 0| CHIP ID | |__|__|_________________||__|__|_________________| | 0| 0| 0| 0| 0| 0| 0| 0|| 0| 0| 0| 0| 0| 0| 0| 0| |__|__|__|__|__|__|__|__||__|__|__|__|__|__|__|__| | 0| 0| Channel ID || 0| 0| Channel ID | |__|__|_________________||__|__|_________________| | Channel Content || Channel Content | |_______________________||_______________________| | 0| 0| Channel ID || 0| 0| Channel ID | |__|__|_________________||__|__|_________________| | Channel Content || Channel Content | |_______________________||_______________________| | 1| 0| CHIP ID || 0| 0| Channel ID | |__|__|_________________||__|__|_________________| | 0| 0| 0| 0| 0| 0| 0| 0|| Channel Content | |__|__|__|__|__|__|__|__||_______________________| | 0| 0| Channel ID || 1| 0| Chip ID | |__|__|_________________||__|__|_________________| | Channel Content || 0| 0| 0| 0| 0| 0| 0| 0| |_______________________||__|__|__|__|__|__|__|__| | 0| 0| Channel ID || 0| 0| Channel ID | |__|__|_________________||__|__|_________________| | Channel Content || Channel Content | |_______________________||_______________________| | 1| 1| 0| 0| 0| 0| 0| 0|| 1| 1| 0| 0| 0| 0| 0| 0| <-- HDI END (C0) |__|__|_________________||__|__|_________________| Fig. 1 - Data stream 16 bit words on a cable from VTM to STT. One 16 bit word in the VTM Module is composed by two 8 bit words, each of them contains information about one HDI. The HDI information is carried out on the fiber through two streams side by side. Considering the stream in figure for HDI 1, the first word gives the SEQUENCER ID (8 bit word, for 140 Sequencers total). The next word in the same stream gives the Sequencer status, the 5 MSB (most significant bit) give the Downloaded status - not described - and the last 3 bits give the HDI number. (there are 8 HDIs per Sequencer). The next word has a 1 0 in the two MSB, that flags the CHIP ID. Every EVEN word - after the Sequencer Header - must contain an address, the address being a CHIP ID if last two MSB are 1 0 , and otherwise a CHANNEL ID if last two MSB are 0 0 (see word number 3 and 5 in the HDI 1 stream in fig). Every ODD word contains data. The word following a CHIP address will contain all ZEROES. (see word number 4 in the HDI 1 stream in fig.) So, word number 5 is a CHANNEL ID and word number 6 is CHANNEL Content. THe end of all Chips belonging to a given HDI is flagged by a C0 (or 1 1 0 0 0 0 0 0 in 8 bit word ), assuming that no channel content nor channel ID will take that value. Channel ID max value can be 127 (7 bits). Channel Content max value can be 255 (8 bits). Above we have described a VTM channel as composed of 16 bit words. I n input to STT (Trigger Card) we need so to split each 16 bit word into two 8 bit words. Each stream representing an HDI will be sent to a separate FIFO, and from there to a given Cluster Finding unit (FPGA) inside the STT Trigger Card. In conclusion, the data stream in input to a given FPGA is constituted of a sequence of 8 bit words, in the exact order as described in fig.1 for one HDI stream. For about timing information, each pair of address-content words is sent every 37.6 nseconds ( read out time per hit for SVX ). The special pair composed by the Header information (Seq ID and HDI+ Status words or CHIP ID and ZEROES) need to be handled in a different way into the FPGA. In particular the HDI ID as well as the CHIP ID needs to be stored and forwarded to the output buffer from the Trigger Card to the Road and Track Fitting Cards. The following pairs (Channel ID and Channel Content) need to be processed by the Cluster Algorithms, in order to calculate the "Centroid" to be buffered then to the same stream as above. I'm not aware that the elements shown in fig. 2 are anywhere. I cannot find them in the TRD , f.ex. in the Block Diagram of Trigger Card (Fig.8). It is clear nevertheless from the same fig. 8 that the input to a single Cluster Finder must be in form of 8 bit words, because there are 8 Cluster Finders for each VTM, and each VTM carries four pairs of HDIs (4 cables in input 16 bit words each). The FIFO units described above in fig. 2 should be in between the VTM box and the Cluster Finder boxes. I need a schematic of the STT Trigger Card that describes its compone nts at that level of detail. _________________________________ | | | V T M CHANNEL | |________________________________| | | | | | | | | \ / \ / V V ____________ ____________ | | | | | FIFO | | FIFO | |___________| |___________| | | | | V V ____________ _____________ | | | | | FPGA | | FPGA | |____________| |___________| Cluster Finder Cluster Finder for HDI 1 for HDI 2 fig. 2 - Conversion from 16 bit words to 8 bit words from VTM to STT, to Cluster Finder in the STC.