Levan's Trigger Work Pages

  • Higgs, DZero, and CTT make cover of Xilinx Xcell Journal (local copy)

  • L1 CTT/PS Digital Trigger Home (including Protocols)

  • L1CTT Commissioning EndGame
  • L1 CFT / CPS / FPS
  • Trigger Digital Front End Meetings
  • L1CTT/PS Oversight Meetings
  • Up-to-date firmware readiness spreadsheet/chart
  • FPGAs for DFE boards
  • L1/L2 timing diagram for CFT/CPSax
  • L1/L2 timing diagram for FPS
  • Some Talk Transparencies
  • "L1CTT Commissioning EndGame" - DØ CTT Commissioning Meeting, April 30, 2002
  • "L1 CTT/PS Protocols Status" - DØ Collaboration Meeting, April 24, 2002
  • "L1 CTT/PS Protocols" - DØ Trigger Commissioning Meeting, April 11, 2002
  • "L1 CTT/PS Firmware Status" - DØ Collaboration Meeting, September 13, 2001
  • "Global Triggers, Prescales, ..." - DØ Shifters Meeting, August 7, 2001
  • "Track and PreShower L1 Digital Trigger" - All DØ Meeting, August 3, 2001
  • "Global Trigger List" - DØ Collaboration Meeting, July 27, 2001
  • "CTTT Status" - DØ Collaboration Meeting, July 26, 2001
  • "DFEA Status & Algorithm" - DØ Collaboration Meeting, July 26, 2001 (transparencies by J. Olsen)
  • "First Look at Trigger Rates" - All DØ Meeting, June 29, 2001
  • "L1CTT/PS Firmware Status & FPGA Specifications" - DØ Trigger Meeting, June 21, 2001
  • "L1CTT/PS Firmware Status" - L1CTT/PS Meeting, May 8, 2001
  • "L1 Tracking Digital Firmware & Installation" - DØ Trigger Meeting, March 15, 2001
  • "L1 Firmware Status" - February'01 Collaboration meeting
  • L1 General
  • L1 Trigger Status - October'00 Collaboration meeting
  • Transparencies
  • CTPT/FPS firmware status summay spreadsheet
  • CTPT/FPS analog and digital front end (block diagram by M. Martin)
  • L1CFT to L1Muon
  • L1CFT tracks to L1Muon
  • AFE Related
  • AFE Boards for Fiber Tracker
  • Skew specifications across LVDS links out of AFE
  • L1/2 FPS Algorithm
  • Clustering
  • L1/L2 timing diagram [ pdf ] - Truncation at DFE DB and COL is a result of L2 timing
  • Truncation Studies: [ html || DØNote 3720 || Talk Transparencies ]
  • A quick look at the effect of the noise in SIFT threshold on FPS cluster multiplicities: [ html ]
  • L1/2 FPS Firmware
  • FPGA's for DFEF
  • Field Programmable Gate Arrays (FPGAs)
  • Xilinx Virtex series
  • Virtex 2.5V FPGA Datasheet
  • Virtex-E 1.8V FPGA Datasheet
  • Virtex-EM 1.8V FPGA Datasheet
  • Using Virtex Block SelectRAM+ Features
  • L1/2 Trigger Data Transfer Protocols
  • FPS Protocols (Other Protocols)
  • L1 FPS Simulation
  • DØ Trigger Simulator Documentation Page
  • Various
  • "Track and Cluster Matching Window Optimization", DØNote 3802