Central Fiber Tracker Commissioning

Please refer to the CFT homepage for a general description of the Central Fiber Tracker project. The CFT Trigger homepage also has a lot of information.

News:

March 13 Certification of AFE boards at Lab 3 continues.

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Introduction
References
Online Notes
Misc. Details

Please contact Thomas Nunneman, nunne@fnal.gov, for more up-to-date information.

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Bryan's homepage

Bryan's CFT homepage

Introduction

Charged particles cause scintillation light to be emitted in the scintillating fibers. The light is channeled by waveguide fibers that shine on VLPC, visible light photon counters. The VLPC send a signal to SIFT chips that discrimnate the signal for trigger and send it to a SVX chip for readout. The Sequencer sends the data over optical link to VRB system (a VME based DAQ).

The SIFT and SVX chips reside on the AFE (Analog Front End) board, and are the current critical point of concern in getting the Run II CFT DAQ chain working.

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References

Here are a few links to information related to data acquisition at D0:

Anderson's Web page, which has some AFE info.

Rack Monitor.

Topic Comment
Online Computing D0's online computing homepage.
Oracle Database
VME VME VITA standards. The Lecroy VME Tutorial
VXWorks Operating system used on the VME embedded processors.
Epics A set of software components and tools for system control; specifically, channel access, which provides network transparent communication between a client and an arbitrary number of servers. D0's Python wrapper of Channel Access. EPICS= Experimental Physics and Industrial Control System.
COMIS An interface to EPICS (COMmunicate with epICS). COOR will talk to COMICS which will in turn talk to EPICS.
Python An interpreted "scripting" language used at D0 for many aspects of the DAQ (data acquisition) Tutorial.
SVX 128 channel readout chip which allows data sparsification (zero-suppression), analog storage, and digitization. Chip has analog pipeline with 4µs of delay to give time to form a trigger. Each of the 128 channels has it's own Wilkenson 8-bit ADC.
SVX Emulator In the absence of working frontend boards, one can fake it, and have the Sequencer readout the SVX emulator board.
SVX Sequencer SVX Sequencers control the SVX chips for data acquisition, and when a trigger occurs, they gather and relay the SVX data to the VRBs.
SVX Sequencer Controller The SVX Controller converts the Serial Command Link commands into the Sequencers format.
1553 Controller Military serial bus. Made by the Fermilab accelerator group. Unfortunately, no manual exists for this module. Essentially, the controller drives the serial bus. Up to 31 RT "remote terminals" allowed.
VRB VME Readout Buffer.
VTM Fiber optic receiver module. It receives the signal from the sequencers and is stuck in the crate of the VRBs, see
VRB manual.
VRBC VME Readout Buffer Controller. Control of the VRBs is provided by the VRBC. Following a Level 1 accept, the VRBC supplies the VRB with a buffer number for data input into the VRBs. Following a Level 2 Accept, the VRBC supplies the VRB with a buffer number for data to output to VME.
VBD VME Buffer Driver. Used to send the data stored in the VRBs to Level 3 after a Level 2 Accept.
SCL Serial Command Link: carries timing information, L1 and L2 trigger decisions, and init requests to all 128 Geographic sections.
MPM Multi-Port Memory
Clock Timing, Sync, and Clock at D0. Contact person: Dan Edmunds.

18.8ns or 53.104MHz, RF Bucket crossing rate.
1113 Buckets are filled, clock can spit out a 1 or 0 for each of the 1113 using a RAM.
Closest Bucket separation, 7RF buckets, 132ns.
Once per turn rate is 47.712KHz, or 20.96µs
TeVSync, or "BOT" used to get precise picosecond times.

Cryo Dan Markley is the contact person.
SIFT Trigger route for the CFT.
Mixing Box Transform fiber data into trigger sectors.
(Final) AFE Analog Front End boards.
VRC Level 3 VME Readout Control; orchestrates getting data from VBDs.
DART A Fermilab data acquisition package.
COOR Program to coordinate client data acquisition requests on the online system.
Examine D0's event monitoring program.
Taker User interface to COOR for data taking.
SDAQ The secondary data acquisition path (elsewhere called "slow control").
SES Significant Event System, message and monitoring system; primary use is to report alarms to DAQ users.

Topic	Comment
Online Computing	D0's online computing homepage.
Oracle Database
VME	VME VITA standards. The Lecroy VME Tutorial
VXWorks	Operating system used on the VME embedded processors.
Epics	A set of software components and tools for system control; specifically, channel access, which provides network transparent communication between a client and an arbitrary number of servers. D0's Python wrapper of Channel Access. EPICS= Experimental Physics and Industrial Control System.
COMIS	An interface to EPICS (COMmunicate with epICS). COOR will talk to COMICS which will in turn talk to EPICS.
Python	An interpreted "scripting" language used at D0 for many aspects of the DAQ (data acquisition) Tutorial.
SVX	128 channel readout chip which allows data sparsification (zero-suppression), analog storage, and digitization. Chip has analog pipeline with 4µs of delay to give time to form a trigger. Each of the 128 channels has it's own Wilkenson 8-bit ADC.
SVX Emulator	In the absence of working frontend boards, one can fake it, and have the Sequencer readout the SVX emulator board.
SVX Sequencer	SVX Sequencers control the SVX chips for data acquisition, and when a trigger occurs, they gather and relay the SVX data to the VRBs.
SVX Sequencer Controller	The SVX Controller converts the Serial Command Link commands into the Sequencers format.
1553 Controller	Military serial bus. Made by the Fermilab accelerator group. Unfortunately, no manual exists for this module. Essentially, the controller drives the serial bus. Up to 31 RT "remote terminals" allowed.
VRB	VME Readout Buffer.
VTM	Fiber optic receiver module. It receives the signal from the sequencers and is stuck in the crate of the VRBs, see
VRB manual.
VRBC	VME Readout Buffer Controller. Control of the VRBs is provided by the VRBC. Following a Level 1 accept, the VRBC supplies the VRB with a buffer number for data input into the VRBs. Following a Level 2 Accept, the VRBC supplies the VRB with a buffer number for data to output to VME.
VBD	VME Buffer Driver. Used to send the data stored in the VRBs to Level 3 after a Level 2 Accept.
SCL	Serial Command Link: carries timing information, L1 and L2 trigger decisions, and init requests to all 128 Geographic sections.
MPM	Multi-Port Memory
Clock	Timing, Sync, and Clock at D0. Contact person: Dan Edmunds. 18.8ns or 53.104MHz, RF Bucket crossing rate. 1113 Buckets are filled, clock can spit out a 1 or 0 for each of the 1113 using a RAM. Closest Bucket separation, 7RF buckets, 132ns. Once per turn rate is 47.712KHz, or 20.96µs TeVSync, or "BOT" used to get precise picosecond times.
Cryo	Dan Markley is the contact person.
SIFT	Trigger route for the CFT.
Mixing Box	Transform fiber data into trigger sectors.
(Final) AFE	Analog Front End boards.
VRC	Level 3 VME Readout Control; orchestrates getting data from VBDs.
DART	A Fermilab data acquisition package.
COOR	Program to coordinate client data acquisition requests on the online system.
Examine	D0's event monitoring program.
Taker	User interface to COOR for data taking.
SDAQ	The secondary data acquisition path (elsewhere called "slow control").
SES	Significant Event System, message and monitoring system; primary use is to report alarms to DAQ users.

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Online Notes

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VBD
VRB
VRBC
Sequencer
Sequencer Controller
1553 Controller
VME Base Addresses
Embedded Processors (vxworks) and EPICS

VBD

Here is a explanation of what must be done to get the VBD correctly initialized:

Address(hex) Mode Value(hex) Comment
6000 Write 000C Write a zero into bit 4 (starting from bit zero) of the control status register 0 (CSR0) to allow the control memory of the VBD to be altered. Bits 2-3 control the DMA timeout value.
6008 Write 0002 Select central tracker mode of readout.
600a Write c0d2,002a event address (pointer)
600c Write c0d0,c0d0 crate id address (pointer)
6010 Write bbf9,bb00 address mode, "d-control", controls access mode of data and word count reads.
6012 Write eded,f900 address mode, "p-control", controls access mode of event number and create ID reads.
6014 Write ff0a,ff08 specify value of upper address bits during parameter value reads.
7000 Write 0032 Here is the null (0) terminated list of the number of word counts, should be one per VRB.
7002 Write 0032
7004 Write 0032
7006 Write 0032
7008 Write 0032
700a Write 0032
700c Write 0032
700e Write 0032
7010 Write 0032
7012 Write 0032
7014 Write 0000
7800 Write 000a Data block pointer list, the first slot to read, etc. One for each VRB. Note: don't forget the space for the VRBC.
7802 Write 0018
7804 Write 000b
7806 Write 0018
7808 Write 000c
780a Write 0018
780c Write 000d
780e Write 0018
7810 Write 000f
7812 Write 0018
7814 Write 0010
7816 Write 0018
7818 Write 0011
781a Write 0018
781c Write 0012
781e Write 0018
7820 Write 0013
7822 Write 0018
7824 Write 0014
7826 Write 0018
6000 Write 0080 Reset the VBD, note should wait at least 200msec to let all of the control registers be updated with the new values.
6000 Write 001c Toggle back bit 4 of CSR0 to disable writing to the control memory of the VBD.
6000 Read ? Why do they read CSR0 back twice????????
6000 Read ?

Address(hex)	Mode	Value(hex)	Comment
6000	Write	000C	Write a zero into bit 4 (starting from bit zero) of the control status register 0 (CSR0) to allow the control memory of the VBD to be altered. Bits 2-3 control the DMA timeout value.
6008	Write	0002	Select central tracker mode of readout.
600a	Write	c0d2,002a	event address (pointer)
600c	Write	c0d0,c0d0	crate id address (pointer)
6010	Write	bbf9,bb00	address mode, "d-control", controls access mode of data and word count reads.
6012	Write	eded,f900	address mode, "p-control", controls access mode of event number and create ID reads.
6014	Write	ff0a,ff08	specify value of upper address bits during parameter value reads.
7000	Write	0032	Here is the null (0) terminated list of the number of word counts, should be one per VRB.
7002	Write	0032
7004	Write	0032
7006	Write	0032
7008	Write	0032
700a	Write	0032
700c	Write	0032
700e	Write	0032
7010	Write	0032
7012	Write	0032
7014	Write	0000
7800	Write	000a	Data block pointer list, the first slot to read, etc. One for each VRB. Note: don't forget the space for the VRBC.
7802	Write	0018
7804	Write	000b
7806	Write	0018
7808	Write	000c
780a	Write	0018
780c	Write	000d
780e	Write	0018
7810	Write	000f
7812	Write	0018
7814	Write	0010
7816	Write	0018
7818	Write	0011
781a	Write	0018
781c	Write	0012
781e	Write	0018
7820	Write	0013
7822	Write	0018
7824	Write	0014
7826	Write	0018
6000	Write	0080	Reset the VBD, note should wait at least 200msec to let all of the control registers be updated with the new values.
6000	Write	001c	Toggle back bit 4 of CSR0 to disable writing to the control memory of the VBD.
6000	Read	?	Why do they read CSR0 back twice????????
6000	Read	?

Questions:

What should be done once and only once after power up of the VBD?
Bits 2-3 of CSR0, what are the DMA timeout value options? (not in documentation))
Lab 3 and DAB access in different ways, why?
What about the 200msec wait after the VBD reset?
Internal PACs = what?
Which of the control parameters can be read back (i.e. hopefully there are not destructive reads). If they can be read back, should to a check.

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VRB

Don't forget, the switches must be set to D0 mode in order to make the VRB work correctly!

The VRB crates are set up as follows:

slot module
1 PPC
4 VBD
14 VRBC
10-20 (not 14) VRB

slot	module
1	PPC
4	VBD
14	VRBC
10-20 (not 14)	VRB

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VRBC

The SCL geographic sector for the VRBC crate is currently 66(hex?).

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Sequencer

The SCL geographic sector for the sequencer crate is currently 5.

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Sequencer Controller

Here is a explanation of what must be done to get the SEQC correctly initialized:

Address(hex) Mode Value(hex) Comment
1 Write 0080,0081,0082 Reset the SEQC.
1 Write 0000,0001,0002 Set the trigger source. SCL,VRBC, and 1553 trigger source, respectively.
1 Read ? ?
2 Write 80 Diagnostic Trigger Register. Write
3 Write 0000-000A Delay of clock to sequencers in 2.5ns steps; 0 least
4 Write 0000-0007 Delay of clock to sequencers in 18.8ns steps; 0 least
5 Write 0000-0007 Delay of clock to sequencers in 132ns steps; 0 least

Address(hex)	Mode	Value(hex)	Comment
1	Write	0080,0081,0082	Reset the SEQC.
1	Write	0000,0001,0002	Set the trigger source. SCL,VRBC, and 1553 trigger source, respectively.
1	Read	?	?
2	Write	80	Diagnostic Trigger Register. Write
3	Write	0000-000A	Delay of clock to sequencers in 2.5ns steps; 0 least
4	Write	0000-0007	Delay of clock to sequencers in 18.8ns steps; 0 least
5	Write	0000-0007	Delay of clock to sequencers in 132ns steps; 0 least

Questions:

What is the base address of the SEQC?
When doing a CSR reset, does the trigger source bit matter?
What values can be read back, and what do they mean?

Essentially, the sequencer controller passes on the NRZ and clock signals to the sequencer. The NRZ is just a serial line strobed by the clock, in which a framed bit string is sent. There are three possible sources of the NRZ signal: the VRBC, the 1553 controller, and the SCL. The VRBC can generate the NRZ signals without conversion whereas the 1553 and SCL signals are converted into NRZ by logic in the SEQC.

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1553 Controller

The 1553 controller is a module which controls a 1553 bus. It was made by the Fermilab accelerator group and, unfortunately, no manual exists. Fritz has written a few programs to test the 1553. The 1553 controller has been setup in the crate with PPC d0olctl36.

setup d0python
type Mscan.py
Mscan.py d0olctl36
MIL.py d0olctl36

One can test either channel 0 of 1 of the 1553 controller, i.e. each controller can drive two different busses each with up to 31 RTs (remote terminals) per bus. One can see which sub-addresses of the RTs on the bus are occupied.

One feature of Fritz's code is that after making a text entry, one must explicitly hit Enter, or the value is not registered.

NOTE: I've found out that doing the "fast" scan can hang the 1553 controller crate. The only way to fix the system is the reset the PPC.

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VME Base Addresses

VRB System Base Addresses (in hex):

Module Base Address Comment
VRBC 480000 .
VRB 0X0000 X is the slot number that module is plugged into; for example, a VRB plugged into slot number 10 would would be assigned the VME base address 0A0000
VBD 380000 .

Module	Base Address	Comment
VRBC	480000	.
VRB	0X0000	X is the slot number that module is plugged into; for example, a VRB plugged into slot number 10 would would be assigned the VME base address 0A0000
VBD	380000	.

Question: what are the base addresses of the SEQ and SEQC?

More precisely:

VBD: 
Short I/O - A16            :     A000 to     BFFF (except at SiDet. SiDet: 6000 to 7FFF)
Standard/Extended - A24/A32: 00380000 to 003FFFFF
    
VRB:
Standard/Extended - A24/A32: 000A0000 to 00150000   

VRBC: 
Short I/O - A16   :              AB00 to     ABFF
Standard I/O - A24:          00480000 to 0048FFFF
Extended I/O - A32:          80480000 to 8048FFFF

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Embedded Processors (vxworks) and EPICS

Examples of computers on the online cluster are: d0ola, d0olb.

From the online cluster, to start talking with the embedded processors:

telnet to t-d0-mch2, a serial line which allows the OS to be downloaded.
login in as ioc; the password you'll just have to know/remember.
connect 11 (for example); then press return a few times and wait.

An example of one of the embedded processors names is: d0olmuo27, which is currently a Motorola 68k and not a PowerPC.

A few vxworks commands:

control-x reboots, or just type in reboot.
dbl gives a list of the objects in the epics database, registered on the processor.
dbgrep for a string.
dbpr to get fields in a record.
From the boot prompt: p and c allow one to print and change the configuration.

A few useful EPICS related files:

xxx.dbt is the template; xxx.dbg is the generator file.
/online/ioc/templates/ is where the epics record files to control the modules can be found.
/online/ioc/ppc/ and /online/ioc/m68k/ are where the power PC and Motorola embedded processor startup files can be found, respectively.
/online/ioc/m68k/mv162/d0olctl01 is where the "cft-startup" and "cft.dbg" files can be found.

Here is a command that one can use to test epics records:

setup d0python
PP.py cft.pp

The file "cft.pp" has a list of the epics records one wants to test.

Don't forget, in order to read via epics, one must first write to the proc field of a record.

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Misc. Details

The clock for LED test (calibration) runs

During a June 7, meeting with Dan Edmundson, he explained the clock and that using trigger framework, one can cut down the readout rate below 21µs, but the clock signal will still always be sent every 21µs. Alan Bross suspects that the 47KHz signal of 2 P.E. LED pulses will not affect the calibration measurement.

Examining data files

From an online computer, one can type dsdump after doing a setup DoRunII to dump raw data. Use the --help option for details. Here is an example: dsdump --raw --byteswap daq_test_0000101756_008@0724173217.raw | more

Look in /online/data/runs to get a run summary.

Here is where one can find a few recent runs online: /buffer/re1/D0Run/done

People

Geoff Savage is the CFT group's liaison to the online controls group.
...

Notes:

Learn a bit more about the VLPC LED calibration scheme.
VLPC bias voltage (16 per cassette). Will the AFE work?
Temp. control.
SXV control.
Goal: readout the SVX Emulator via Sequencer through the VRB System and analyze the data. Then stereo boards and finally the final AFEs.
How do tune in the SXV to get the max amount of charge?
Mike Utes' homepage, lot of nice stuff.
Lyn and Mendosa are the engineers on the VRB project.
Talk with Harold Fox, he is the silicon guy doing silicon commissioning.
Talk to Scott Synder.

Lab 3 VLPC Daq

To take a look at Volker's Lab 3 daq, do the following:

setup d0cvs
cvs checkout vlpcdaq
setup d0python
cd vlpcdaq/daq
edit flags.py so offline only (to test.....)
python master.py

Unfortunately, the lab 3 daq can't be directly used for the online commissioning, yet there is useful stuff in it.

SMT daq

To take a look at Harald Fox's SMT daq, do the following:

setup d0cvs
cvs checkout onl_smtcalib
source smt_setup (or setup onl_smtcalib if defaults OK)
dbgui.py

To get the most up to date code, it is best to look in Harald's directory on the online machines.

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Send comments and suggestion to brsmith@fnal.gov

Last modified: March 13, 2001