DØ Calorimeter Data and Code Status

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Last Update: September 17, 2002 - L. Groer

Significant Events or Periods for Calorimeter Data Taking

Major changes   L1 CAL changes
Date Store First Run Last Run Condition/change
August 28/29, 2002 1711 163063   08/28: Added a capacitor and changed a resistor on all 1152 BLS boards (except L+M boards in the ECS). This should reduce the "bounce" seen by the L1CAL trigger on a L1 accept.
08/29: Installed FPGA v29 in all 13 T&C cards.
August 15, 2002 1663 161972   Installed FPGA code v28. Only use 41 L1 SCA cells; fix race condition; changed synch between ADC + T&C; fix bug in ADC digitization when gets SCL init.
Greatly reduced out-of-synch problem (mixed events) observed for crates 0x44, 0x47 and 0x4A.
August 14, 2002 09:40 1661 during 161916   Installed FPGA code v28 (in crate 0x47 only) to cure frequent hang ups of this crate. See logbook entry
Aug 1, 2002 161025   Timing adjustment of L1Cal digitization by 56 ns (to sample at peak of pulse)
July 31, 2002 17:34 1613 161020   FPGA v27 fixed and installed. Repairs multiple readouts of 0x4C.
July 23, 2002 1569 160361   L1 CAL reference set #3 fixed, reducing L1 trigger rates
July 5, 2002 13:55       Latest version of PIB-eproms installed: PibRampB6 version 8
- Corrects the update of current pattern number in Pib memory
- Wait function implemented that allows a wait up to 10000 iterations
June 30, 2002 1482 158527   preliminary EM calibration adjustment for L1 CAL (HAD not adjusted because it was fine)
June 30, 2002 1482 158527   Started permanent multi-buffer running.
June 26, 2002 1464 158062   Changed zero suppression threshold online from 2.5 to 1.5
June 21, 2002 1448 157713   Extension of L1 trigger eta to 2.4.
June 18, 2002 1434 157476   First store after shutdown. Changed to FPGA code version 26. Installed all SBC's.
June 3, 2002 1396   155605 June Shutdown.
May 24, 2002   154935   Switched from Run 1 to Run 2 electronics for central Trigger Towers (|eta|<0.8)
May 17, 2002 1332 154569   Turned on readout of TCC in crate 0x4c.

Run Ranges from Bob Kehoe that are good (i.e. do not exhibit event mixing comparing the L1 trigger energy to precision readout). 

>161972 (Aug 15)                  Good
 158527 (Jun 30)-161971 (Aug 15)  Bad
 158041 (Jun 25)-158064 (Jun 26)  Bad
 157573 (Jun 19)-157576 (Jun 19)  Bad
 157478 (Jun 18)                  Bad (single buffered but data looks very wierd)

Special Runs or Data Sets

Date Run Conditions Purpose
Sep 6, 2002 11:35 163392 Calorimeter special run with online zero suppression at 2.5 Study threshold effect
Aug 25, 2002 11:35 162594 Standard data run but reprocessed with 1.5 and 2.5 offline threshold. Study threshold effect
Aug 23, 2002 19:29 162523 Calorimeter special run with single buffer mode Study event mixing

Reconstruction Code Versions

Dates Version Features
Sep 17, 2002 p11.12.01
  p11.12.00 Modification of noise simulation in pileup to use single gaussian rather than double gaussian.
Specialized versions s11.00.00-x.x where made to run with different thresholds (x.x = 0.0, 1.5, 2.0, 2.5)
  p11.11 Should be good for both MC and data.
First release with offline zero suppression (default: 2.5)
  p11.10 Good for MC, but not for data (MC fix messed up real data)
  p11.09 first release with NLC, good for data but not for MC
Feb 2002 p10.15 Fix of bug where ilayer = 8 (CC MG) was empty in the MC for all previous p10.xx versions (xx=05-14)

Timing and Control FPGA Versions

Version Installed Features
29 Aug 29, 2002
  • Fix ADC busy and reset ADC on ADC crate timeout (which should not happen)
28 Aug 14-15, 2002 The major changes in this version are (from Dean's log entry August 14, 2002 11:43:27 PM,
sequence number: CAL/Log - CAL_Log - 114969
  • We now use only 41 "peak" cell adddress (6-46), instead of the 42 previously used.
  • Fixed a race condition in 4 crates where the timing counter used to measure the length of time charge is held until it is allowed to be readout was not being reset to zero on a new trigger. Thus those crate incorrectly reported an error.
  • Changed slightly they way I sense that the ADC is not in sync with the T&C card. This might help the "0x51" hangs...might not.
  • Fixed a bug which would sometimes cause the ADC to get confused if an SCL init accidently happened while digitization was in progress.
27 July 31, 2002
  • Added timer for L2 hold (in 133 usec units)
  • L2 state bits should be working
  • Crates 0x44, 0x47 and 0x4A have mixed events when run in multibuffer mode.
26 June 2002 during shutdown
  • First version for new T&C boards 3.0
  • Crates 0x44, 0x47 and 0x4A have mixed events when run in multibuffer mode.

Notes

Date Created: Wednesday, August 14, 2002 9:20:49 AM CDT
Date Saved: Wednesday, August 14, 2002 11:30:08 AM CDT
Category - Topic - sequence number: CAPTAIN_Shift/Log - CAPTAIN_Log - 114758
Operator(s): Gene Fisk
Keyword(s): :CAPTAIN:

09:40 We have paused Run 161916 at 299499 events to allow D. Schamberger to down- 
load some new CAL timing readout control FPGA code in crate 47 that will test 
a fix to a "too close timing" problem. Also downloaded software to correct an 
SMT bias voltage problem with x62. 

09:42 Run 161916 resumed. 

10:40 End Run 161916 with events to change pre-scales as we are now at L = 9 E30. 
---------------
Date Created: Wednesday, August 14, 2002 9:38:55 AM CDT
Date Saved: Wednesday, August 14, 2002 9:40:21 AM CDT
Category - Topic - sequence number: CAL/Log - CAL_Log - 114745
Operator(s): Marc Hohlfeld
Keyword(s): :CAL:

Dean changed FPGA code for Crate 47 to version 28. This should cure the 
0x51 and 0x8010 problems in the STATUS field.
This page maintained by Leslie Groer
Last modified: Tue Sep 17 23:37:06 CDT 2002