\contentsline {figure}{\numberline {1}{\ignorespaces Simplified diagram of the calorimeter data flow path. }}{3}
\contentsline {figure}{\numberline {2}{\ignorespaces The calorimeter part of the data flow and control in Run 2. }}{4}
\contentsline {figure}{\numberline {3}{\ignorespaces Distribution of preamplifier input cable length for all channels (top), CC channels only (middle) and EC channels only (bottom). This is for the Run 1 cables. }}{6}
\contentsline {figure}{\numberline {4}{\ignorespaces Distribution of preamplifier input cable length for all channels (top), CC channels only (middle) and EC channels only (bottom). This is for the Run 2 cables. }}{7}
\contentsline {figure}{\numberline {5}{\ignorespaces Schematic of the calorimeter preamplifier circuit. }}{9}
\contentsline {figure}{\numberline {6}{\ignorespaces Log-Log plot of the measured frequency transfer functions for an uncompensated preamplifier (lower curve) and a preamplifier compensated for a detector capacitance of 667 pF (upper curve). }}{12}
\contentsline {figure}{\numberline {7}{\ignorespaces Log-Log plot of the measured frequency transfer function for a preamplifier compensated for a detector capacitance of 4450 pF. }}{13}
\contentsline {figure}{\numberline {8}{\ignorespaces Pedestal widths in ADC counts for Run 2 prototype preamplifiers, scaled for expected factors to compare directly with Run 1 preamplifiers. }}{13}
\contentsline {figure}{\numberline {9}{\ignorespaces Pairwise correlation coefficient of pedestals for Run 2 prototype preamplifiers. }}{14}
\contentsline {figure}{\numberline {10}{\ignorespaces Ratio of frequency transfer function of preamplifier species A with and without 30 $\Omega $ input termination. }}{15}
\contentsline {figure}{\numberline {11}{\ignorespaces Ratio of frequency transfer function of preamplifier species G with and without 30 $\Omega $ input termination. }}{15}
\contentsline {figure}{\numberline {12}{\ignorespaces Distributions of channel pedestal width and pairwise correlation coefficient between channel pedestals, measured in the 5000 channel test station using different preamplifier power supplies. }}{19}
\contentsline {figure}{\numberline {13}{\ignorespaces Schematic diagram of the Baseline Subtractor (BLS) system.}}{22}
\contentsline {figure}{\numberline {14}{\ignorespaces Schematic diagram of the sequence of operations performed with the level-1 SCA buffers.}}{23}
\contentsline {figure}{\numberline {15}{\ignorespaces The shaping and trigger pickoff circuit. }}{24}
\contentsline {figure}{\numberline {16}{\ignorespaces The $\times $1 and $\times $8 gain stages. A fast clamping circuit is part of the OPamp, and protects the SCA circuit from voltages outside its valid operating range. }}{24}
\contentsline {figure}{\numberline {17}{\ignorespaces Output voltage pulse of the Run 2 calorimeter preamplifier and Shaper filter combination for a triangular current pulse input. }}{25}
\contentsline {figure}{\numberline {18}{\ignorespaces First stage trigger adder schematic. Input resistor values are chosen to match the EM or hadronic channels involved. }}{26}
\contentsline {figure}{\numberline {19}{\ignorespaces Final trigger adder and differential cable driver. }}{27}
\contentsline {figure}{\numberline {20}{\ignorespaces Schematic diagram of a Switched Capacitor Array (SCA).}}{28}
\contentsline {figure}{\numberline {21}{\ignorespaces Block diagram of the timing and control FPGA chip.}}{34}
\contentsline {figure}{\numberline {22}{\ignorespaces Flow chart for the write address generator. The notation is different from that of the text: SCA1 is SCA0 and SCA2 is SCA1.}}{36}
\contentsline {figure}{\numberline {23}{\ignorespaces Block diagram of the level-1 processor.}}{38}
\contentsline {figure}{\numberline {24}{\ignorespaces Block diagram of the timing and control signal pattern generator.}}{39}
\contentsline {figure}{\numberline {25}{\ignorespaces Calibration system for Run 1.}}{41}
\contentsline {figure}{\numberline {26}{\ignorespaces Simulation set-up used to study the Run II calibration system.}}{42}
\contentsline {figure}{\numberline {27}{\ignorespaces Schematic view of the proposed calibration system for Run II.}}{43}
\contentsline {figure}{\numberline {28}{\ignorespaces Schematic view of the a) Pulser Motherboard ; b) Active Fanout.}}{45}
\contentsline {figure}{\numberline {29}{\ignorespaces Schematic of the ``switch'' circuit which is located on the active fanout and which generates the calibration pulse. On the lower left corner are located the 2 resistors and the 2 capacitors mentionned in the text are located in the lower left corner of the figure.}}{46}
\contentsline {figure}{\numberline {30}{\ignorespaces Frontal view of a 4608-channel preamplifier box.}}{51}
\contentsline {figure}{\numberline {31}{\ignorespaces Breakdown of cost estimates.}}{55}
\contentsline {figure}{\numberline {32}{\ignorespaces Breakdown of cost estimates (continued).}}{56}
\contentsline {figure}{\numberline {33}{\ignorespaces Breakdown of cost estimates (continued).}}{57}
\contentsline {figure}{\numberline {34}{\ignorespaces Breakdown of cost estimates (continued).}}{58}
\contentsline {figure}{\numberline {35}{\ignorespaces Milestones for the calorimeter upgrade.}}{59}
\contentsline {figure}{\numberline {36}{\ignorespaces Organization chart for the calorimeter upgrade project.}}{60}
\contentsline {figure}{\numberline {37}{\ignorespaces Manpower requirements for the calorimeter upgrade.}}{61}
\contentsline {figure}{\numberline {38}{\ignorespaces Distribution of preamplifier input cable lengths for EC channels. This is for the Run 1 cables. }}{63}
\contentsline {figure}{\numberline {39}{\ignorespaces Distribution of preamplifier input cable lengths for EC channels. This is for the Run 2 cables. }}{64}
\contentsline {figure}{\numberline {40}{\ignorespaces Schematic of the power regulator and test circuit part of the preamplifier tester. }}{66}
\contentsline {figure}{\numberline {41}{\ignorespaces Schematic of the test pulse generator part of the preamplifier tester. }}{68}
\contentsline {figure}{\numberline {42}{\ignorespaces Specifications of the Vicor switching power supply.}}{70}
\contentsline {figure}{\numberline {43}{\ignorespaces Output voltage of the Vicor switching power supply in a magnetic field parallel to its length.}}{71}
\contentsline {figure}{\numberline {44}{\ignorespaces Output voltage ripple of the Vicor switching power supply in a magnetic field parallel to its length.}}{72}
\contentsline {figure}{\numberline {45}{\ignorespaces 68-pin Plastic Leaded Chip Carrier for SCA Packaging.}}{73}
\contentsline {figure}{\numberline {46}{\ignorespaces The two types of SCA packages.}}{74}
\contentsline {figure}{\numberline {47}{\ignorespaces The pinout for the normal SCA.}}{75}
\contentsline {figure}{\numberline {48}{\ignorespaces The pinout for the reversed SCA.}}{76}
\contentsline {figure}{\numberline {49}{\ignorespaces SCA write pulse width test.}}{77}
\contentsline {figure}{\numberline {50}{\ignorespaces SCA voltage scan test near the ground rail.}}{78}
\contentsline {figure}{\numberline {51}{\ignorespaces SCA voltage scan test near the positive power voltage of 5 V.}}{79}
\contentsline {figure}{\numberline {52}{\ignorespaces The deviation of the SCA response from a straight line.}}{80}
\contentsline {figure}{\numberline {53}{\ignorespaces Input signal (trace starting at -0.5 V), output signal (trace starting at 0 V), and the difference of the (output voltage - input voltage)$\times 10$ for a good SCA device.}}{81}
\contentsline {figure}{\numberline {54}{\ignorespaces Input signal (trace starting at -0.5 V), output signal (trace starting at 0 V), and the difference of the (output voltage - input voltage)$\times 10$ for a bad SCA device.}}{82}
\contentsline {figure}{\numberline {55}{\ignorespaces Input signal (100ns risetime trace), output signal (slower risetime trace), and the difference of the input voltage - output voltage for a good SCA device.}}{83}
\contentsline {figure}{\numberline {56}{\ignorespaces Input signal (100ns risetime trace), output signal (slower risetime trace), and the difference of the input voltage - output voltage for a SPICE simulation.}}{84}
\contentsline {figure}{\numberline {57}{\ignorespaces Input signal (1$\mu $s risetime trace), output signal (slower risetime trace), and the difference of the output voltage - input voltage for a good SCA device.}}{85}
\contentsline {figure}{\numberline {58}{\ignorespaces Input signal (1$\mu $s risetime trace), output signal (slower risetime trace), and the difference of the input voltage - output voltage for a SPICE simulation.}}{86}