D-Zero Level 2 GSTM Page

The GSTM, or General System Test Module, from the perspective at D-Zero is a replacement module for the French TXGLINK sender which is now out of commision. I t was brought out of storage at FCC and is a product of an ESE-SVX project. At D0 we are using this card with a TXGLINK daughter card to create G-link data for the purposes of testing our FIC modules, and determining thier status. The original documentation from ESE is available. However this documentation does not include anything on the TXGLINK daughter card that is in use at D0. Other useful documents are here. Here is a picture of the GSTM.

Modifications that need to be in that document that we have found are below.

• The test register gives an "ID" for the daughter card. It needs to be said that at least for the TXGLINK daughter card, this ID is set by jumpers manually and reads 0xffffff09 if they are not set.

• In Table 6, where the bits of the mode register are described, the document states that G-link flag select is bit 9, we found that this is incorrect and FLAGSEL is actually bit 11. Also bit 10 is FF, or fill frame type.

• It also should be mentioned that as we have set the GSTM up at the test stand, the T1-Mode is actually the 16/20 bit select mode. Setting this bit (7) high, sets the mode to 20 bit mode.

• In the control register, bit 31 will be reffered to as the control port, it is a very important bit.

Guide to Programming

The programs we have written for the GSTM can be found on D0NTMSU1 at the test stand in the c:\work\gstm directory. There is a program that runs on windows and uses a Bit3 card for a VME interface which was written with visual C++, and also a program that runs on the alpha. The procedure for sending data is outlined below.It is not explained in the ESE documentation, but is implemented in the programs we have written.

The following five steps are required for the initial setup of the GSTM. It syncs the TXGLINK with the RXGLINK. Enabling a bit means writting a 1 to it, and disabling a bit means writting a 0.

1. Reset the GSTM. (enable bit 0 in the control register)

2. Enable the port. (T1 in our case. Bit 3 in the Mode register)

3. Enable 20 bit mode. (T1 Mode in our case. Bit 7 in the Mode register)

4. Enable port control (bit 31 in the control register).

5. Disable port control, enable port control again, and disable port control again.

6. The GSTM is now ready to send data

7. Repeat steps 1-3.

8. Load the data you want to send to the FIFO. This is acomplished by writting to register T1 over VME. When you write the data you must always have bit 22 set in the data. This is acomplished by adding 0x400000 to whatever data you load. This sets an active low line called CAV* (control available) high and leaves the active low line DAV* low which alows the data to be clocked into the FIFO on the reciever side when the data is transmitted. At the end of the data, you must include a line that stops the receiver from clocking data. This line is 0x2000000. This sets CAV* (Control available) low and DAV* high and reciever no longer clocks data into its FIFO. If this is not set the reciever will continue to clock into its FIFO, the last word that was sent.

9. Disable port control. This step alows the data with the 0x400000 in it to be clocked into the FIFO.

10. Start transmission. (bit 5 in the control register)

11. Enable port control. The data will then be clocked into the FIFO's.

12. Disable port control.

Steps 7-12 can be repeated to send multiple events.

We have found that the GSTM we are in possesion of has something wrong with the FIFO's where they cannot be filled up to the 16K depth stated in the manual. Also we have not been able to make the LoopOver transmitting described in the manual work.

For Fast reference, the registers are listed below with the modifications listed above included.

The Control Register

The Mode Register

Page created by Jason Wennerberg on 8-2-2001

Last Updated on 8-3-2001