Digital Board programming for the L1 FPS

1. Digital Board Algorithm
  • The last (up-to-date) version is version 202. This is the one described in D0 note 3697.
  • Location:
  • On my PC (DPSB04): My_computer::User Disk D:/ /lucotte/2.FPGA/Version_200/Version_202
  • On D0server1:
    D0server1/USERS/lucotte/Altera/Version_202
  • Different versions are available:
  • Version 100: 101/102/103 use a 4 equal-size subsectors / module
  • Version 104: is taken from Jamieson example, and shows an example of the use of pipelines
  • Version 202: use 6 subsectors / module, corresponding to EC eta segmentation

    • 2. Documentations and list of contacts
  • D0 note 3697 [20p.] (to be posted)
    "Digital Board Algorithm for the L1 FPS Trigger"
  • Compressed ps file: (ps.gz)
  • Trigger Architecture: F. Borcherding, M. Martin -- FPS Protocols
  • VHDL experts: Jamieson Olsen, Kin Yip.

    • Email : lucotte@fnal.gov